I was asked to using the data in a bmp file as the simulation input for a verilog module and write the simulation output to a new bmp file, so that they can compare the two different bmp file to check the correction of verilog module.
I succeeded in read, but met some problems in writing.
module testsub1;
integer fout;
initial
begin
fout=$fopen("C:/Users/gyz/Pictures/testout1.bmp","wb");
$fwrite(fout,"%u",8'h42);
$fclose(fout);
end
endmodule
The output is supposed to be 8'h42. But the real output is
enter image description here
Needless zero occur. I guess it is because verilog write row binary at least 16n bit at a time, n >=1. So I change the sixth line into $fwrite(fout,"%u",24'h424d5f);,the result becomes
enter image description here
There is still a redundant zero. How can I make the program just output 8 bits each time.
