variable-sized parameter array in verilog

Question

I am observing odd behaviour when simulating a design with a parameter array in (system)verilog.

Here is my module interface:

module src_multi
#(
    parameter NUM_DEST = 4,                  
    parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1] //problematic line
)
(
    ...
);

and the instantiation of that module in the testbench:

src_multi
#(
    .NUM_DEST(3),
    .DEST('{13,12,8})
)
src_src1_outbun
(
      ...
);

The idea is basically I want DEST to be an array of numbers, and the number of entries should depend on NUM_DEST. However, when DEST is declared as shown above but not initialized:

parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1]

modelsim always reads the value 0 from DEST, as if it was full of zeroes.

if I initialize the array as follows:

parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1] = '{0,1,2,3}

I get a runtime simulation error:

# ** Fatal: (vsim-120) Illegal Concat. Number of elements doesn't match with the type.

this is because in my instantiation, I want the array to be of size 3. So I tried initializing it with size 3 (as follows), and that works perfectly!

parameter NUM_DEST = 3,
parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1] = '{0,1,2}

but this forces me to only use one size for that array, but I want it to have a variable size.

How can I use a variable-sized parameter array in (system)verilog?

mohsaied mohsaied · Accepted Answer · 2015-05-26T20:59:49

Turns out this is a modelsim bug. This input yields different results on two different modelsim versions:

parameter NUM_DEST = 4,
parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1]

modelsim 10.3d = correct

modelsim 10.1e = wrong

To fix it in all cases, we can initialize the array with the parametrized number of inputs NUM_DEST as follows:

parameter NUM_DEST = 4,
parameter [N_ADDR_WIDTH-1:0] DEST [0:NUM_DEST-1] = '{NUM_DEST{1}}

variable-sized parameter array in verilog

2 Answers