Verilog Testbench constant exp and pram compilation and simulation errors

Question

Source Code:

module SingleOneBit(N,T);

parameter integer w; //width or number of inputs N

input wire [w-1:0] N;
output wire T;   

wire[w*(w-1):0] N1; //for anding all possible combinations of 2 bits 
wire R; // for oring all tha ands. If R = 1 then N contians more than one bit with value 1
wire RS; //ors all the bits of the input. Used for checking if there is one bit with value 1 or all 0s
wire R1; // not of R;


buf(R, 0); //initialy R should be 0;
buf(RS, 0); //initialy RS should be 0;

genvar i, j;

generate

for(i = 0; i<w; i=i+1) begin

or(RS,N[i],RS);

for(j = i+1; j<w; j=j+1) begin

and(N1[(i*w)+j], N[i], N[j]);
or(R,N1[(i*w)+j],R);

end    
end

endgenerate

not(R1, R);
and(T,RS,R1);  

endmodule

Testbench Code:

`include "C:/Users/Muaz Aljarhi/Google Drive/Muaz/Hardware_Designs/Verilog Course/SingleOneBit.v"

module SingleOneBit_tb();

integer n = 5;

reg[n-1:0] N;
wire T;

SingleOneBit sob(.N(N),.T(T));
defparam sob.w = n;

initial begin

$monitor("N = %b, T = %b",N,T);  



end  

endmodule

Compilation of this Verilog Testbench code yeilds the following errors:

** Error: C:/Users/Muaz Aljarhi/Google Drive/Muaz/Hardware_Designs/Verilog Course/SingleOneBit_tb.v(7): Range must be bounded by constant expressions. ** Error: C:/Users/Muaz Aljarhi/Google Drive/Muaz/Hardware_Designs/Verilog Course/SingleOneBit_tb.v(11): Right-hand side of defparam must be constant.

How to declare a variable or a constant experssion which can be changed within a test bench? I tried using parameter but parameters are not variables which can be changed. Thanks in advance

Edit: Do I have to declare different instantiations of the module with possibly different input reg variables or there is another way?

I also tried this:

SingleOneBit sob(.N(N[0]),.T(T));
defparam sob.w = 32'd5;

but simulating, using modelsim yeilds the following:

# ** Error: (vopt-2293) The parameter 'w' in the instance ('/SingleOneBit_tb/sob') of ('SingleOneBit') is declared without a value,
# 
# and the instantiation does not provide a value for this parameter.

How to avoid getting this error at simulation? Thanks again.

Unn Unn · Accepted Answer · 2015-06-15T16:23:02

As parameters are compile-time (technically elaboration-time) constants, you cannot have them change during the course of execution. Thus, the first error in which sob.w was set to n is not valid as n cannot be determined to be a fixed value during the elaboration phase (part of compiling the entire design, before simulation can take place).

The second error is a result of the declaration of SingleOneBit module sob not defining hte w parameter. While you define it later with a defparam, you need to provide some default value of w. You can do this in the module itself by changing the declaration of w to include a default value:

parameter integer w = 32'd5;

As you seem to want to test various widths of this module, I dont see a way around not declaring multiple widths of this module. Of course, you can use a generate statement to produce these module of various width compactly; but I very sure there isnt any way of changing the parameter in the middle of simulation.

EDIT: I forgot to mention that the defparam construct might be removed from the language (IEE1800-2009 and IEEE1800-2012 both list it as something that might be eliminated in the future), so you should avoid using it to allow your code to be compatible with future tools.

Verilog Testbench constant exp and pram compilation and simulation errors

2 Answers