I'm getting the vsim-3033 error in ModelSim when I try including a sub module into a testbench for simulation. All code compiles fine (according to modelsims 'check marks'). The code here is obviously Verilog. I've seen the question "answered" a couple of times - however the explanation at this stage goes over my head.
The exact error is as follows:
vsim -voptargs=+acc work.NGateTB
# vsim -voptargs=+acc work.NGateTB
# Loading work.NGateTB
# ** Error: (vsim-3033) C:/Users/user/Desktop/testitems/ngateTB.v(7): Instantiation of 'MUT' failed. The design unit was not found.
#
# Region: /NGateTB
# Searched libraries:
# C:/Users/user/Desktop/testitems/work
# Error loading design
I'm new to ModelSim and I have no idea how to fix it and the issue I'm having is that a lot of the explanations are too "technical" at this stage for me to follow as I'm relatively new to this environment. (please - explain what I'm doing wrong in a way a six years old would understand - and how to fix the issue - and more importantly what it is caused by).
I know this is basically a problem related to "finding the called module" - however I do not know how to fix it. I've tried adding the project root directory into the (project window) -> left click -> properties -> Verilog & SystemVerilog -> include directory...
The code is as follows:
module ngate(A, B);
input A;
output B;
assign A = !B;
endmodule
the test bench code is:
`include "ngate.v"
module NGateTB();
reg A;
wire B;
MUT ngate (A, B);
endmodule
When I comment out the MUT ngate(A,B); line the issue disappears. So I know this has to do with something in how ModelSim does includes in simulation. (And not to mention the code basically isolates this as the only cause as far as I can tell). The only other issue is the include syntax perhaps - however I am not sure on this. All files are located in the 'root' of the project space - with the only subfolders being those generated by modelsim in a "work" folder.
When I simulate the ngate module by itself - I have no issues - and it works fine. Currently both items are in the top level of the design with no subfolders (virtual or otherwise). It's only when I include a submodule into another module does an issue appear.
I am using modelsim Altera starter edition 10.1.b. - if that matters.
I hate to admit it - but the IDE has me stumped here.