Verilog : Large Bus OR synthesis

Question

I'm looking to do a logical OR of a bus.

The working code:

parameter Width = 8;
wire my_bus [Width-1:0];
wire bus_or = (my_bus[0] || my_bus[1] || ... || my_bus[Width-1])

That works fine but is entirely unsuitable for large busses (i.e. 64 bit)

I have seen: (from here)

wire bus_or = |my_bus;

However this just complains with the error: Illegal operand of unary operator '|' and Illegal right hand side of continuous assign.

Interestingly the syntax:

wire bus_or = |{my_bus[0], my_bus[1], ..., my_bus[Width-1]}

Works fine, despite the concatenation creating a bus, with the original un-split object being a bus to start with...

We are using generate blocks to create various signals, wires, registers etc with the aim of extensible parameterised code. It seems a shame if syntax for a bus OR is so error prone.

What i'd love is something as simple as wire bus_or = |my_bus;

Sorry. Very simple answer!!!

The wire bus_or = |my_bus; notation works fine when the bus is declared as a vector BUT NOT when its an array: see here.

Morgan Morgan · Accepted Answer · 2013-04-16T15:24:32

You are not defining a N bit bus but a collection of 1 bit busses.

You really want :

parameter Width = 8;
wire [Width-1:0] my_bus ;

That should allow the following to work.

wire bus_or = |my_bus;

NB: it is good practise to make constants upper case. WIDTH instead of Width. May be add some semantics to it as well, W_DATA or W_CONTROL etc.

Verilog : Large Bus OR synthesis

2 Answers