Synthesis error in Verilog

Question

I am trying to implement the FatICA algorithm in verilog. I have written the whole code and till simulation it shows no error but when I try to synthesize the code it gives an error stating " ";" expecting instead of".""

I am using four floating point modules for arithmetic calculation and I have generated 1000 instances of sum, sqrt ... etc using for loop for the in between calculations.Following is the code for generate

genvar s;

generate
    for(s=1;s<=4000;s=(s+1))

    begin:cov_mul_ins 
            Float32Mul cov_mul  (.CLK(clk),
                        .nRST(1'b1),
                        .leftArg(dummy_14),
                        .rightArg(dummy_15),
                        .loadArgs(1'b1)
                        );
    end
endgenerate

Now I am accessing the individual instances using the Dot operator

 for(d=1;d<=2;d=(d+1))

begin
   for(e=1;e<=2;e=(e+1))
    begin
       for(c=1;c<=1000;c=(c+1))
          begin
        if((d==1)&&(e==1))
            begin
            dummy_14=centered_data_copy[d][c];
            dummy_15=Parent.centered_data_float_trans[c][e];

        #10 ***cov_mul_ins[c].cov_mul***(.CLK(clk),
                             .nRST(1'b1),
                             .leftArg(dummy_14),
                             .rightArg(dummy_15),
                             .loadArgs(1'b1),
                             .product(cov_temp[c][1])
                             );

I would be grateful if someone could pin point the error I am making.Thanks!

@osgx I think there is no error in the generate statement but I am not sure if I am acessing the instantiated modules in the proper way.I tried searching for it on web but didn't found anything. Then, there was an example in samir palnitkar's book which had similar array instantiation and so I followed that. While simulation it is not showing any error but while synthesizing it gives and error. — optimus

Marty Marty · Accepted Answer · 2011-08-04T09:53:10

Couple of things to note:

Out of module references can't be synthesised. This means that you can't "peek inside" instantiated modules to look at nets or call functions if you want that code to be synthesisable. It's grand for testbenches though.
Your attempted function call has a delay on it, which will be ignored, ie #10 cov_mul_ins[c].cov_mul ( ... );

I can see your thinking in a softwarey lets-put-everything-in-a-class-and-call-methods way. This is perfect for testbenches, but synthesis will complain, as you've seen. When it comes to hardware, well, you need to think of the hardware - ask youself which blocks you need to build to run your algorithm. For example, if your algorithm needs 30 multiplies on each input sample, then you need either 30 instances of a multiplier, or one multiplier and sequence your 30 operations through it. Or 15 multipliers, each doing 2 multiplications per sample period, or 10 multipliers doing 3 etc...

Synthesis error in Verilog

2 Answers