Synthesis error on a CASE statement in Verilog

Question

I m new in Verilog and I would like to know your opinion about an error I get when trying to synthesize the part of my code cited below:

input [31:0] A;
reg [31:0] X,Y;
reg [15:0] width;
input action;       

always@*
begin

  width= A [31:16]; 
  if (action==1)    
  begin    
    case (width) 
      16'b0: X=0;
        default: 
          begin
            for (i=32; i>=width+1 ; i=i-1)
              X[i]=0;
            for (i=width; i>=0; i=i-1)
              X[i]=1;
          end 
    endcase 
    Y=X >> 1;
  end
end

I m using Cadence synthesis tool and the error that i get is in this part of my code saying :

Index 'X[-1]' is not within the valid range of the declaration [31:0]

which i don't understand because even if width=0 i have a special case that should not involve the for loop. i also tried increasing the limits to width +2,width +1 and then shift the quantity X by 2 ..but also got the same error.

Thank you in advance!

Greg Greg · Accepted Answer · 2014-08-11T16:19:45

I don't see how i could be -1, but it is possible for it to be greater than 31 which is out of range. There are couple of synthesis issues:

i=32 is already out of range for X[31:0]. Its MSB is 31.
i will go out of range when width > 31. width is a 16-bit unsigned value, meaning its maximum value is 65535 (i.e. 2¹⁶-1) and its minimum is 0.
Synthesis requires loops to static unroll. This means the number of loops must be constant. Variables such as width cannot be in the loops condition.

A synthesis-able for loop will look as follows:

for (i=31; i>=0; i=i-1)
  X[i] = (width>=i);

I'm assuming the width= A [31:16]; above the always block is a copy past typo as it is illegal syntax. I'm also assuming there are no additional assignments on width, X, Y, or i outside of the always block. Otherwise there are additional errors.

Synthesis error on a CASE statement in Verilog

2 Answers