define a constant in verilog (for synthesis)

Question

I'm writing some Verilog code for synthesis. My block has a reg type A, that has to have always the same value. In order not to have syntax errors, I wrote the following:

module dig_block ( OUT, OUTN, in , OUTlevelL, mode_1, mode_0 , rst);
    output [11:0] OUT, OUTN;
    input [11:0] in, OUTlevelL;
    input  mode_1, mode_0, rst;  
    reg [11:0] OUT, OUTN;

    reg [11:0] A;   
    integer B; 


    always @(ck or rst) 
    if(~rst)
        begin
            A =512;   
            B =in[10:0];

            case  ({mode_1, mode_0})  
            2'b00:  begin     
                    OUT=A-B;   
                    OUTN=~OUT;
                end

            default:   begin  
                OUT=OUTlevelL;
                OUTN=~OUT;
                end
            endcase
        end
    else
        begin  
            A =512;
            B =0;     
            OUT =0;
            OUTN=1;
        end 
endmodule

Is it possible to define A before "always"? I don't know what is the common practice for quantities that has to be fixed and are not inputs, nor outputs. I don't want unnecessary ports placed during synthesis. Thank you very much for your help!

ck is not declared and the way you wrote your always block, your code will be treated as pure combinational logic with no flops. — Greg
Pretty sure always @(ck or rst) should be always @(posedge ck or posedge rst). — Morgan

Sourabh Sourabh · Accepted Answer · 2016-03-11T03:53:45

You can define it as Local parameter. This will confine its scope inside this module only.

module dig_block ( OUT, OUTN, in , OUTlevelL, mode_1, mode_0 , rst);
        output [11:0] OUT, OUTN;
        input [11:0] in, OUTlevelL;
        input  mode_1, mode_0, rst;  
        reg [11:0] OUT, OUTN;

        localparam [11:0] A=512;

define a constant in verilog (for synthesis)

1 Answers