verilog syntax error near always

Question

I'm new to Verilog. When I try to write code for a finite state machine. I get :

[Synth 8-434] mixed level sensitive and edge triggered event controls are not supported for synthesis

Here is my code:

module controller1(x, clk, s, v);
    input x;
    input clk;
    output s;
    output v;

    reg [2:0] state;
    reg s;
    reg v;

    always @ (negedge clk or x) begin
      case (state)
          3'b0 : begin
                  state <= x ? 3'b1 : 3'b10;
                  s = x ? 0 : 1;
                  v = 0;
                 end
          3'b10 : begin
                   state <= x ? 3'b11 : 3'b101;
                   s = x ? 0 : 1;
                   v = 0;
                  end    
          3'b1 : begin
                  state <= 3'b11;
                  s = x ? 1 : 0;
                  v = 0;
                 end
          3'b101 : begin
                    state <= 3'b100;
                    s = x ? 1 : 0;
                    v = 0;
                   end
          3'b11 : begin
                   state <= x ? 3'b111 : 3'b100;
                   s = x ? 0 : 1;
                   v = 0;
            end
          3'b100 : begin
                    state <= 3'b0;
                    s = x ? 1 : 0;
                    v = 0;
                   end
          3'b111 : begin
                    state <= 3'b0;
                    s = x ? 0 : 1;
                    v = x ? 1 : 0;
                   end
      endcase      
    end
endmodule

The question is:

A sequential circuit has

one 1-bit input (X)

a clock input (CLK)

two 1-bit outputs (S and V)

X represents a 4-bit binary number N. The 4-bit number will input one digit a time and start from the least significant bit (LSB).

S represents a 4-bit binary number equal to N + 3. The LSB of S will be output first

when the fourth bit input occurs, V = 1 if N + 3 is too large to be represented by 4 bits; otherwise, V = 0.

circuit always resets after the fourth bit of X is received. Assume the sequential circuit is implemented with the following state table.

The outputs are (S,V). All state changes occur on the falling edge of the clock pulse.

If my code has problem to get the required result, please point out. Thanks！

No semi-colon after the "reg v" declaration (just before always)? — happydave
@happydave oh, thank you for pointing out this mistake! But there still is error around the always. Vivado says "[Synth 8-434] mixed level sensitive and edge triggered event controls are not supported for synthesis" I have limited understanding in writing the condition for always @() statement — Jiang

nikunj nikunj · Accepted Answer · 2016-04-10T03:19:19

Basically every always block is describing a group of flip-flop, a group of latch, or a block of combinational circuit.

In your code you have mixed edge and level sensitivity by using 'negedge clock' and 'x'. If your FSM is sensitive to only falling edge of clock then remove 'x' from sensitivity list of always block.

Mixed sensitive list of levels and edges is not synthesizable, because a flip-flop cannot be edge-tiggered and level-triggered at the same time. Check this link: Synthesis of `always` blocks

verilog syntax error near always

1 Answers