Verilog: Using casex for synthesis

Question

I'm looking to implement a parallel case block that will check the value of a 16-bit register. In some cases, I need it to check for all 16 bits. However, in others, I only need to check a few. Is casex suitable in this scenario? If you hadn't already inferred, it is to be synthesized.

It's part of a control matrix for a microprocessor. It's a Moore machine connected to an instruction register. Instructions are 16 bits wide. For some instructions, such as mov, the machine states are exactly the same, except the register/memory addressing is different. The instruction contains the information about what register or memory it's referencing, so I do not need to explicitly have a case for every possible instruction.

For example, if my opcode was 1111, and the remaining 12 bits were addressing, I could simply use a case for 16'b1111xxxxxxxxxxxx.

I'd like it to be parallel, and so I'm not using if-else statements. I'm unsure if this will work the way I intend it to. Any suggestions would be appreciated.

Just because I'm curious, why do you need to check all 16 bits in this case statement? I would think this case statement would just look at the 4 bit opcode and decode that. You could do further decoding in separate logic. Unless your opcode changes size depending on the operation..? — Russell
Yep, that was just an example. The opcode does change depending on operation. — Shreyas
@Russell Although, I've not actually thought about the instruction set yet. A five or six bit opcode followed by the remaining ten or eleven bits can be useful instead of checking for all sixteen bits. All it's going to have to do is read different instruction formats correctly. — Shreyas

Ari Ari · Accepted Answer · 2014-07-30T17:54:27

Yes, you could either use casex or casez.

Examples from IEEE 1800-2012:

with casez, you can use ? for don't care values:

logic[7:0] ir;
casez(ir)
8'b1???????: instruction1(ir);
8'b01??????: instruction2(ir);
8'b00010???: instruction3(ir);
8'b000001??: instruction4(ir);
endcase

The following is an example of the casex statement. It demonstrates an extreme case of how donot-care conditions can be dynamically controlled during simulation. In this example, if r = 8'b01100110, then the task stat2is called.

logic[7:0] r, mask;
mask = 8'bx0x0x0x0;
casex(r ^ mask)
8'b001100xx: stat1;
8'b1100xx00: stat2;
8'b00xx0011: stat3;
8'bxx010100: stat4;
endcase

Verilog: Using casex for synthesis

1 Answers