how to define the input and output for the interface in systemverilog

Question

Here I have a simple example below.

module A(o,clk,rst,i);
  output o;
  input i,clk,rst;
  ...
endmodule

and here is an interface class definition below.

interface my_if(input bit clk);
  logic o,rst,i;
  wire clk;

  clocking cb@(posedge clk);
    input o;         // why input here ?
    output i,rst;    // why output here ?
  endclocking
  ...
endinterface

My question is how to decide the signal inside cb is input or output ??

Thank you !

I mean if I may understand in this way that the direction of signal is just opposite between the module and interface ? — Rocky Zheng
usually to define inputs and output views for an interface, modports are used. clocking block can be used to construct modports. The IO views are used to connect interface to different modules with different IO ports. — Serge
Thanks Serge. So the input/output view for each signals defined in interface class could be alternative, which depends on the modules we want to connect — Rocky Zheng

dave_59 dave_59 · Accepted Answer · 2018-03-20T07:07:36

There are many uses of input/output in SystemVerilog, which can be confusing.

For ports, they the flow of data across a boundary. For a clocking block, they represent whether a signal is passively being sampled, or actively driven. Depending on the situation, it is perfectly reasonable to have a port declared as an output, and the same signal declared as a clocking block input.

how to define the input and output for the interface in systemverilog

1 Answers