verification testbench ports need directions or not necessary?

0
votes

I am having a question regarding declaring signals in verification testbench/interface. As i am told in the textbook, i suppose to declare each signal with directions in my testbench or interface, but strangely i can still get correct results without doing that. I can just declare all signals as "logic", and feed them to the correct input/output ports of my DUT.

So I am confused if input/output declaration is necessary for a verification testbench? verification testbenches are not necessarily to be synthesizable, aren't them? even some examples in my book didn't write the testbench with input/output ports. Sometimes i see plainly "module test();" all signals in the module are declared as "logic".

can someone give some detailed explanations on this? Do I must declare directions for my signals in my testbench?

1
system-verilog
logic is a datatype in verilog, it does not indicate the port direction. You can have logic input or logic output to specify the port direction. - Karan Shah

1 Answers

3
votes

The top-level modules in a testbench have no ports, and therefore no directions to specify. A lower level module needs ports if you want to pass signals across the module boundary up to the higher level module and a port declaration requires a direction. Simulators do not care whether a module description is being used for a testbench or the design and might ignore the specified direction. Synthesis tools require correct signal directions.

SystemVerilog's interface construct is slightly more complicated because it is a collection of signals, each with the potential to be used as a port. A modport construct used within an interface specifies the signals that be used as ports and their directions. As with module ports, modports require directions as part of the port syntax.