I am new to systemverilog. I learned the functionality of "interface" to connect testbench and DUT but what I am thinking is why do I need to connect these two? Can't I simple pass the testcases generated by testbench to my DUT via "mailbox"? If not, then why?
0
votes
You can use mailbox to exchange data between two process inside testbench, but not between DUT and testbench, since mailbox is not synthesizable
- csehydrogen
A SystemVerilog interface is a container of wires and/or variables. Interfaces are synthesisable, so, if your DUT is a subblock, then it may have a so-called interface port and so you would be able to connect the interface right to it. If not, you'd connect the DUT ports to the wires/variables inside the interface using hierarchical naming. A SystemVerilog mailbox is a software construct. Information is put in and gotten out by calling tasks and functions (get, put, try_put etc). DUT's don't interact with the outside world via tasks and functions; they have ports, usually of type logic.
- Matthew Taylor
But why do I have to worry about synthesis when I am verifying a design? Suppose I have my design module is ready with me which has to be tested. All I need to do is generate stimulus in testbench and pass them to DUT. Is it necessary for "something- which passes the signal to DUT" to be synthesizable?
- Payal
1 Answers
1
votes
They are two different concepts. A mailbox is a type of class—a data type. An interface is a collection of instances of data types, and that collection is used a possible port to DUT. Conceivably, any data type can be used as a port of a module, but RTL synthesis does not handle class data types.
You can certainly use a mailbox in your testbench to pass stimulus transactions to your DUT, but something (usually a component called a driver) has to translate the transaction object to a set of pin wiggles to your DUT.
