UVM : How to connect multi dimensional arrays in virtual interface?

3
votes

I have 5 SRAM instances (== 5 different 2-D arrays) in DUT (all in verilog). I want to do backdoor loading on these arrays from a UVM testbench. There are multiple drivers on SRAM array, either from DUT itself or from testbench (from testbench it is mainly backdoor access using $readmemh). Now, i wanted a handle of these arrays into UVM testbench. So, i created a virtual interface which has local memory array and instantiated the interface 5 times. Trouble is, how to connect DUT SRAM array with the array in virtual interface? I need to make a weak connection so that there is no contention when DUT drives the array.

Can anyone suggest how to connect multi dimensional arrays in UVM testbench and not have strong drivers?

1
arraysverilogsystem-veriloguvm
It might be helpful to add some code to the question. How does your interface look like? What have you tried so far? - Tudor Timi

1 Answers

0
votes

Since the was no Code, it was a bit hard to understand the question.

My understanding is that you are trying to initialize several 2D array. In case you are using Modelsim, there is a very simple way for initialization through TCL scripts. Indeed this tool considers all 2D array as memory and it has a TCL function to load a contents from file to these memory arrays.

Here is an example of the TCL code to do so:

mem load -i Startup_Memories/sram.hex -format hex -fillradix symbolic -skip 0 /orpsoc_testbench/dut/ram_wb0/ram_wb_b3_0/ram0