SystemVerilog Interface array with different parameters

Question

I've got a parametrized interface with clock input. For example :

interface itf # (PARAM1 = 16, PARAM2 = 8)(input logic clk);

This interface has a modport called "slave".

My module takes an array of this interface as an input (modport "slave").

module MyModule #(NB_ITFS = 4)(... itf.slave itfs[NB_ITFS]...);

In a testbench module for MyModule, I would like a generic code that is able to test different values of NB_ITFS.

Question : how to create my array of interfaces for MyModule instanciation (taking into account the fact that elements have different parameters) ?

For example, I tried to use a generate statement :

module testbench()
...
generate
    genvar i;
    for (i = 0; i < NB_ITFS; i++)
    begin : interfaces
        itf #(.PARAM1(PARAM1_TABLE[i]), 
              .PARAM2(PARAM2_TABLE[i])) itf_inst (.clk(clk));
    end
endgenerate
...
endmodule

But in this case, the interface array is interfaces[xxx].itf_inst (and .slave if I want to select the "slave" modport) and the instanciation of MyModule using interfaces[NB_ITFS].itf_inst.slave raises an error.

I also tried without success: - a generic definition itf itf_inst[NB_ITFS] (.clk(clk)); and tried to modify the parameters using defparam inside a generate block - "virtual interface" feature

Any suggestion ?

Matthew Taylor Matthew Taylor · Accepted Answer · 2017-02-27T12:19:57

How about putting your generate inside another interface:

interface itfa #(NB_ITFS = 4)(input logic clk);
  ...
  generate
    genvar i;
    for (i = 0; i < 4; i++)
    begin : interfaces
      itf #(.PARAM1(i), 
            .PARAM2(i)) itf_inst (.clk(clk));
    end
  endgenerate
  ...
endinterface

and then using that as the interface to MyModule:

module MyModule #(NB_ITFS = 4)(itfa itfs);
  ...
endmodule

Then you can instanciate the outside interface (itfa) and connect it to an instance of MyModule in the usual way:

module testbench;
  ...
  logic clk;
  ...
  itfa #(4) itfa_inst (.clk(clk));
  ...
  MyModule #(4) MyModule0 (.itfs(itfa_inst));
  ...
endmodule

https://www.edaplayground.com/x/254C

SystemVerilog Interface array with different parameters

1 Answers