How to use structural unit?

Question

I write my verilog code using simple adder(inbiult in xilinx itself) but i want to replace it using RNS adder whose code i already made and it gives module RNS(clk,rst,a,b,c) where a,b are input of rns adder and c is output.

And my code for which i am using simple adder is given below.In my code i am using enable ,for that i have to use always block....but in structural modelling(when i call RNS adder) how to deal with this enable?

module output_adder_8(enable,s089,s318,s175,s250,s289,s118,s075,s350,s189,s218,s375,s050,s389,s018,s275,s150,r1,r3,r5,r7);
input enable;
input [13:0] s089,s175,s250,s318,s289,s118,s075,s350,s189,s218,s375,s050,s389,s018,s275,s150;
output reg[15:0] r1,r3,r5,r7;
reg [11:0] c,d,e,f,g,h,i,j;
//reg [3:0] countp=4'b0000;

always@*
begin
 if (enable)

 c<= s089+s318;
 d<= s175+s250;
 r1<= c+d;
 e<= s289+s118;
 f<= s075-s350;
 r3<=f-e;
 g<= s218-s189;
 h<= s375+s050;
 r5<=g+h;
 i<= s018-s389;
 j<= s275-s150;
 r7<=i+j;


end
endmodule




module shift_adder_8a( clk, z0, s018, s050, s075, s089,enable0 );

 input clk;
 input [12:0] z0;
 output reg [13:0] s018;
 output reg [13:0] s050;
 output reg [13:0] s075;
 output reg [13:0] s089;
 output reg enable0;


// temp reg declaration
reg [3:0] count0=4'b0000;
reg [13:0] d01,
           d02,
              d03,  
              d04,
              d05,
              e01,
              e02,
              e03,
              e04;

always @(posedge clk )
 begin 
      d01 <= z0<< 3;
      d02 <= z0 << 4;
      d03 <= z0 << 6;

        if (count0==4'b0110)
        d04 <= e01 << 1;
        d05 <= e02 << 1;        
        e01 <= d01 + z0; 
        e02 <= d02 + e01;
       e03 <= d03 + e02;        
        e04 <= e02 + d05;
        s018 <= d04;
        s050 <= d05;
        s075 <= e04;
        s089 <= e03;
        enable0<=1'b1;


   end

Unn Unn · Accepted Answer · 2015-03-23T16:00:16

If you want to use your own adder design instead of whatever builtin or equivalent the synthesis+compliler tool gives you, you need only instantiate your module instead of use the + operator. To retain your enable line, you can simply have a separate combinational block (either always @* or assign) which passes the output through if enable is on or 0s on the output if enable is off. Heres an example:

module( enable, clk, rst, a, b, c );
  input clk;
  input rst;
  input enable;
  input [15:0] a;
  input [15:0] b;
  output [15:0] c;

  wire [15:0] adder_out

  // Your adder
  RNS rns_adder( .clk(clk), .rst(rst), .a(a), .b(b), .c(adder_out) );

  // Enable line
  assign c = (enable) ? adder_out : 16'b0;

endmodule

NOTE: Don't use non-blocking assignment (<=) in always @* blocks, use blocking assignment (=)

How to use structural unit?

1 Answers