carry lookahead using structural verilog

Question

I am working on 4 bit carry lookahead I am using structural verilog. I am confused as I am instantiating 4 partial full adders what to declare as input and what as wire and where does the sum go? I know this is easy problem for some, but I spent some time trying to find my errors. The way I implement pfa's (partial full adder) I have a,b,carry as input and p(a * b) g(a xor b) as output. Here is where I get confused, what is the carry? Is it input or is it a wire ? Below is my code, thank you!

module pfa(a,b,c,sum,p,g);  //A one PFA. I need 16 of them5
    //wire w;
    //reg a,b,c;
    //wire sum,p,g;
    input a,b,c;
    output sum,p,g;

    xor (w,a,b);     //repeated P. May need it may not. 
    and (g,a,b);  //Gi
    xor (p,a,b);   //Pi
    xor (sum,w,c);  //sum 
endmodule
                //input    output   
module fourBitPFA(A,B,Cin,P,G,Carry);
    input [3:0] A,B;
    input Cin;
    output [3:0] S;
    output Cout;    
    wire [3:0] P,G,carry;
    wire p0,g0;
    wire b1,b2,b3;
    wire w,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
    wire c1,c2,c3,c4;

        pfa PFA0(A[0],B[0],Cin,P[0],G[0],Carry[0]),
            PFA1(A[1],B[1],C[1],P[1],G[1],C[1]),    
            PFA2(A[2],B[2],S[2],P[2],G[2],C[2]),
            PFA3(A[3],B[3],S[3],P[3],G[3],C[3]);
        //propagate
        and (p0,P[3],P[2],P[1],P[0]);

        //GENERATE
        and (w,P[3],G[2]);
        and (w1,P[3],P[2],G[1]);
        and (w2,P[3],P[2],P[1],G[0]);
        or (w,w1,w2);
//CLA 


        and (w3,P[0],Cin);
        or (c1,G[0],w3);
        and (w4,P[1],G[0]);
        and (w5,P[1],P[0],Cin);
        or (c2,G[1],w4,w5);
        and (w6,P[2],G[1]);
        and (w7,P[2],P[1],G[0]);
        and (w8,P[2],P[1],P[0],Cin);
        or (c3,G[2],w6,w7,w8);
        and (w9,P[3],G[2]);
        and (w10,P[3],P[2],G[1]);
        and (w11,P[3],P[2],P[1],G[0]);
        and (w12,P[3],P[2],P[1],P[0],Cin);
        or(c4,w9,w10,w11,w12);
endmodule

sharvil111 sharvil111 · Accepted Answer · 2015-11-28T17:46:22

wire elements must be continuously driven by something, and cannot store a value. Henceforth, they are assigned values using continuous assignment statements.

reg can be used to create registers and other sequential elements in procedural blocks. Thus, it can store some value.

reg elements can be used as output within an actual module declaration. But,reg elements cannot be connected to the output port of a module instantiation.

Thus, a reg can drive a wire as RHS of an assign statement. On the other way round, a wire can drive a reg in as RHS of a procedural block.

For clear idea about declaration of reg or wire, refer the image below. By default, input ports are reg and output ports are wire.

Module connection

Remember, wire can only infer to combinational logic, while reg can infer to either combinational or sequential logic.

Here, in look ahead carry generator, everything is combinational circuit. So, declaring wire for sum, p and g variables; is feasible.

For carry, when two single bit numbers are added in binary, if both are 1's, then addition results in a two bit number. So, the MSB is considered as carry.

Side Note: In this case, using behavioral modelling may be advantageous from coding point of view.

Also, instiatiating gates requires a gate name. So, use xor x1(sum,w,c); where x1 is the gate instance name. This applies to all the gate instances.

Instiatiating single module multiple times requires name of module at every instance name. As follows:

    pfa PFA0(A[0],B[0],Cin,P[0],G[0],Carry[0]);
            pfa PFA1(A[1],B[1],C[1],P[1],G[1],C[1]); 
// and so on

carry lookahead using structural verilog

1 Answers