Verilog always inside a generate block is throwing error

Question

I am trying to execute addition through using ripple carry adder using for loop and I wanted the operation to be performed only at posedge of clock. For doing so, I have used a generate block and used for loop inside the generate block. If I use without always statement it would work fine, but when I add the always block it would result in error when simulating. Below is the code:

genvar i;
generate
    always @(posedge clk)
    for(i=0;i<=31;i=i+1) begin : generate_block         
        fulladd f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));

    end
    end

endgenerate

Here fulladd is a different module.

Below is the error that I am getting when simulating:

   Error-[IBLHS-CONST] Illegal behavioral left hand side
   add32.v, 36
   Constant Expression cannot be used on the left hand side of this assignment
   The offending expression is : i
   Source info: i = 0;


   Error-[IBLHS-CONST] Illegal behavioral left hand side
   add32.v, 36
   Constant Expression cannot be used on the left hand side of this assignment
   The offending expression is : i
   Source info: i = (i + 1);


   Error-[SE] Syntax error
   Following verilog source has syntax error :
   "add32.v", 37: token is '('
        fulladd 
   f1(.sum(sum[i]),.cin(cout1[i]),.a(b[i]),.b(temp[i]),.cout(cout1[i+1]));

add32.v is the design module name. I have used synopsis vcs. I am new to verilog programming, please explain the underlying concept which I have mistaken. Thanks in advance

Displayname Displayname · Accepted Answer · 2016-10-31T10:43:02

Addition logic & registering signals should be treated separately. Pull the relevant input & output signals from adder and register them separately at posedge.

see this CLA adder implementation code for reference

I have implemented a generic ripple carry adder as below.

// ripple_carry_adder.v
// NOTE : I have registered the outputs only. Inputs are asynchronous. 

`timescale 1ns  / 10 ps
module ripple_carry_adder 
            #(  parameter COUNT = 32                  // width of RCA port
            )
                (      
                    input  clk,rst,                 
                    input  Carry_in,            
                    input  [COUNT-1:0] A, B,
                    output reg [COUNT-1:0] Sum,
                    output Carry_out
                );

reg [COUNT-1:0] Carry,Cout; 
assign Carry_out = Cout[COUNT-1];

always@(posedge clk or posedge rst)
begin
    if (rst)
        begin
            Carry  = 'b0;
            Sum    = 'b0;
            Cout   = 'b0;
        end
    else
        begin   
            Cout    = ((A & B) | ((A ^ B) & Carry));
            Sum     = (A ^ B ^ Carry);
            Carry   = {Cout[COUNT-1:1],Carry_in}; 
        end
end
endmodule

Verilog always inside a generate block is throwing error

2 Answers