What are the various constructs that one could use to break out of an “always” block in Verilog?

Question

For instance in this thread - How to NOT use while() loops in verilog (for synthesis)?, Brian Carlton mentions that instead of using for and while loops in Verilog, one should use an always loop. I was wondering what are the ways to break out of an iteration if a particular condition is satisfied. I was wondering if the following could be used :

always @ (posedge clk or var == 3)`

Where var is a variable in the module or block?

For instance, how would I convert the following code into something which can be synthesized by XST.

    //******************************************************
//Check whether randp is prime or not
//******************************************************
for(i = 0; i < 100; i = i+1)
begin
    assign PRIME_CHECK = randp;
    assign sqroot = PRIME_CHECKED;
for(i = 0 ; i <= sqroot ; i=i+1)
    begin
        if((sqroot%i) == 0)
        begin
            break;
        end
    end
    break;
    randp = RANDP;
end

dave_59 dave_59 · Accepted Answer · 2016-06-26T15:36:26

There is no way to break out of always block. You are declaring the existence of a process that is always there. Hardware cannot be dynamically created or destroyed. What you can do is wrap the code around a condition and branch around it. But if you are writing synthesizable code, the always block must always follow the coding rules for sequential or combinational logic.

BTW var is a reserved keyword in SystemVerilog, so don't use it.

--Updated-- Now that you have added the software code you want translated to hardware, that is a different question. Before you can break out of this loop, you need to partition the loop into clock cycles of a state machine. Then a break out of a loop becomes a jump in your state machine.

What are the various constructs that one could use to break out of an “always” block in Verilog?

1 Answers