Verilog Matrix multiplication error in synthesis

Question

I am writing a 32row by 32col multiplication on Verilog. I have tried to synthesize the code but it gives an error saying the signal is connected to multiple drivers. The code below is uncomplete but gives the same error. I am new to Verilog and I don't get know how to fix this. Could you give suggestions on how to fix this. I am using Xillinx version 14.5 and the FPGA is virtex 5.

I am using inbuilt multipliers and inbuilt adders. Here is the code:

module matrixMult(Arow, Bcol,CLK, AxB);
    input [1023:0] Arow;
    input [1023:0] Bcol;
    input          CLK;
    output [31:0] AxB;

     wire [1023:0] Arow;
     wire [1023:0] Bcol;
     wire [1024:0] ab;
     wire [1024:0] AxB;


     // multiplication
     ip32Mult a1b1(CLK, ab[1023:992], Arow[1023:992],Bcol[1023:992]);
     ip32Mult a2b2(CLK, ab[991:960], Arow[991:960],Bcol[992:960]);

     // addition // no clock enable
     ip32Add ab1( AxB[31:0], ab[1023:992], ab[991:960]);

endmodule

The Error:

ERROR:Xst:528 - Multi-source in Unit <matrixMult> on signal <ab<992>>; this signal is connected to multiple drivers.

Additional information: How the ip32Add looks like

module ip32Add (
  clk, s, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
  input clk;
  output [31 : 0] s;
  input [31 : 0] a;
  input [31 : 0] b;
  ....

How the ip32Mult looks like:

module ip32Mult (
  clk, p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
  input clk;
  output [31 : 0] p;
  input [31 : 0] a;
  input [31 : 0] b;
  ...

Answer 1

The ip32Add header has a clk pin but the ab1 instance does not. Therefore with connect by order, AxB[31:0] is connected to the clk and ab[1023:992] is connected to the output s. ab[1023:992] also connected to the output p if instance a1b1. Thereby ab[1023:992] having two drivers. There are probably warnings for instance ab1 such as width mismatch and b not being connected.

I'd recommend connecting your ports by name (eg: .portname(netname)) instead of by order. Order does not matter with connect by name and is more explicit. If clock doesn't matter but the pin does exists, ab1 should look something like this:

ip32Add ab1( .s(AxB[31:0]), .a(ab[1023:992]), .b(ab[991:960]), .clk() );

Answer 2

A bit too long for a comment but not to be considered a full answer. Could you redefine you module using the modern style:

module matrixMult(
  input [1023:0] Arow,
  input [1023:0] Bcol,
  input          CLK,
  output [31:0]  AxB );


 wire [1024:0] ab;

You had this line :

 wire AxB;

Which not sure if it would cause it to be 1 bit or if the preceding statement (32bits wide) would win.

It would be helpful if the question could also show headers for :

ip32Mult
ip32Add

As the error suggest the ab connection might be connected to two drivers rather than an input and an output.