Verilog module in Xilinx "signal never used" error

Question

I have a Verilog program where I have to model an ALU that can add, subtract, check for equality and divide by 2. My code:

module alu(
input wire [7:0] sw,
 output reg [2:0] s, 
 output reg cout
 );

reg co1, co2;

always @(*) begin 

    if(~sw[6] & ~sw[7]) begin 
    s[0] = sw[0] ^ sw[3] ^ 1'b0; 
    co1 = (sw[3] & 1'b0) | (sw[0] & 1'b0) | (sw[0] & sw[3]);

    s[1] = sw[1] ^ sw[4] ^ co1; 
    co2 = (sw[4] & co1) | (sw[1] & co1) | (sw[1] & sw[4]);

    s[2] = sw[2] ^ sw[5] ^ co2; 
    cout = (sw[5] & co2) | (sw[2] & co2) | (sw[2] & sw[5]);
    end

    else if(sw[6] & ~sw[7]) begin
    s[0] = sw[0] ^ ~sw[3] ^ 1'b1; 
    co1 = (~sw[3] & 1'b1) | (sw[0] & 1'b1) | (sw[0] & ~sw[3]);

    s[1] = sw[1] ^ ~sw[4] ^ co1; 
    co2 = (~sw[4] & co1) | (sw[1] & co1) | (sw[1] & ~sw[4]);

    s[2] = sw[2] ^ ~sw[5] ^ co2; 
    cout = (~sw[5] & co2) | (sw[2] & co2) | (sw[2] & ~sw[5]);

    end
        \\more code
end

endmodule

I am getting this warning for 'co1' and 'co2'

signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.

I am confused with the warning because from my understanding 'co1' and 'co2' are used to assign something. Overall when I run it on my board I get no outputs at all.

these 2 are neither input or output, you use them to have a better view on what is happening. for verilog however it is not needed. The program will compile your output based on what is on the inputs (sw) that make your co1 and co2. Meaning you can just ignore these warnings or rewrite your logic to only inclide your inputs — Axel Bouttelgier
So the fact that my program is not outputting anything is some other error in my program? It is not related to the warnings? — ecain
possibly, you could test your logic by simulating it. youtube.com/watch?v=_wFdoxq5YyE hopefully this wil tell at what point things go wrong — Axel Bouttelgier
Yes, it is a top module. I think it might be an issue with the clock. The simulation works fine. — ecain
May be co1 and co2 have got removed after synthesis due to optimization. And hence it has informed you in terms of warning — Karan Shah

ecain ecain · Accepted Answer · 2017-07-20T21:56:53

0

votes

So this ended up being a non-issue. They were removed after synthesis.

Verilog module in Xilinx "signal never used" error

1 Answers