The code is synthesized properly but when I try to simulate it only lda changes from 0 to 1. The rest of the control signals remain just the same. The eqz signal never changes from x. The rest of the signals remain in 0 state. I have tried everything.Can anyone tell me where I have gone wrong?
Test bench
module multiplier(input clk, start, [15:0]datain , output done);
wire eqz, lda, ldb, ldp, clrp, decb;
mul_datapath D(eqz, clk, lda, ldb, ldp, clrp, decb, datain);
mul_control C(done, lda, ldb, ldp, clrp, decb, clk, start, eqz, datain);
endmodule
Data path
module mul_datapath(eqz, clk, lda, ldb, ldp, clrp, decb, datain);
input clk, lda, ldb, ldp, clrp, decb;
input [15:0] datain;
wire [15:0]x, y, z, bout;
output eqz;
PIPO1 P1(x, clk, lda, datain);
PIPO2 P2(y, clk, ldp, clrp, z);
ADD A(z, x, y);
COUNT CNT(bout, clk, ldb, decb, datain);
COMP com(eqz, bout);
endmodule
PIPO register A
module PIPO1(x, clk, lda, datain);
input clk, lda;
input [15:0] datain;
output reg [15:0] x;
always @(posedge clk)
if(lda) x<= datain;
endmodule
PIPO register B
module PIPO2(y, clk, ldp, clrp, z);
input clk, ldp, clrp;
input [15:0] z;
output reg [15:0]y;
always @(posedge clk)
begin
if(clrp) y<= 16'b0;
else if(ldp) y<= z;
end
endmodule
Adder unit
module ADD(z, x, y);
input [15:0]x, y;
output reg [15:0]z;
always @(*)
z = x + y;
endmodule
Counter to decrement B
module COUNT(bout, clk, ldb, decb, datain);
input clk, ldb, decb;
input [15:0] datain;
output reg [15:0]bout;
always @(posedge clk)
begin
if(ldb) bout <= datain;
else if(decb)
bout <= bout -1;
end
endmodule
Comparator to compare B to zero
module COMP(eqz, bout);
input [15:0] bout;
output eqz;
assign eqz = (bout==0);
endmodule
Control path
module mul_control(done, lda, ldb, ldp, clrp, decb, clk, start, eqz, datain);
input clk, start, eqz;
input[15:0] datain;
output reg lda, ldb, ldp, clrp, decb, done;
reg [2:0]state;
parameter S0=000, S1=001, S2=010, S3=011, S4=100;
always @(posedge clk)
begin
case(state)
S0 : if(start) state<= S1;
S1 : state<=S2;
S2 : state<= S3;
S3 : begin if(eqz) state<=S4; else state<=S3; end
S4 : state<= S4;
default : state<= S0;
endcase
end
always @(state)
begin
case(state)
S0: begin lda = 0; ldb = 0; ldp = 0; clrp = 0; decb = 0; done = 0; end
S1: begin lda = 1; ldb = 0; ldp = 0; clrp = 0; decb = 0; done = 0; end
S2: begin lda = 0; ldb = 1; ldp = 0; clrp = 0; decb = 0; done = 0; end
S3: begin lda = 0; ldb = 0; ldp = 1; clrp =0; decb = 1; done = 0; end
S4: begin lda = 0; ldb = 0; ldp = 0; clrp = 0; decb = 0; done = 1; end
default : begin lda = 0; ldb = 0; ldp = 0; clrp = 0; decb = 0; done = 0; end
endcase
end
endmodule
