MIPS Pipeline with and without Forwarding

Question

I am looking at the number of stalls in the following MIPS code with and without forwarding. I am trying to get a better understanding of when the data is needed in the datapath.

lw $10, 0($4)
sw $10, 24($5)

With forwarding, I get the following with the understanding that the value going into register 10 from the load word instruction is available after the memory stage, and that value is needed by the store word instruction before its memory stage. Hence, there are zero stalls.

F D E M W
  F D E M W

If there is no forwarding, register 10 will not have the correct value from the load word instruction until it is written in the first half of the clock cycle in the write back stage.

Is it correct to say that the store word instruction needs the correct value of register 10 in the second half of the clock cycle in the decode stage, producing the following two stalls:

F D E M W
  F F F D E M W

Or is it that the store word instruction needs it in the execute stage producing this sequence of two stalls:

F D E M W
  F D D D E M W

I guess I'd like a way of phrasing this in my head to better my understanding.

LadyDee852 LadyDee852 · Accepted Answer · 2015-12-17T14:44:03

Without forwarding, the load word instruction will have register 10 updated after the 1st half of the clock cycle in the write back stage. The store word instruction will need to read that value in register 10 in the second half of the clock cycle in the decode stage, producing the following 2 stalls in the decode stage:

F D E M W
  F D D D E M W

MIPS Pipeline with and without Forwarding

1 Answers