MIPS pipeline cycles

Question

I'm trying to understand how the following MIPS code in a pipelined datapath would execute.

  lw  $4, 100($2)
  sub $6, $4, $3
  add $2, $3, $5

The MIPS instruction set has 5 stages (fetch, decode, execute, memory access, write back).

The answer is: 8 cycles but I'm having difficulty understanding why. Here is what the pipeline could look like (incomplete).

  C F   D   E  M   WB
  1 lw
  2 sub lw       
  3 add sub lw
  4 add sub  x  lw
  5     add sub    lw
  6         add sub
  7
  8

Questions: Why the x (stall?) at 4 and 5? How do I come up with the cycles including 7 and 8?

The stalls are presumably because the instruction needs the result of the previous one. — Jester

Phil Miller Phil Miller · Accepted Answer · 2014-10-22T02:04:32

We'd need to have the full datapath details from your textbook or assignment (I assume) to be sure. Here are some possibilities:

The sub instruction stalls for 2 cycles before entering Execute, because it needs to wait for the lw result to finish Writeback
The add instruction stalls until sub is finished Writeback, again because it's waiting for a result.

The detail that's relevant to both of these possibilities is when results from a given instruction become available to later dependent instructions. Does your datapath have register bypass of some sort? Are results in Writeback available the same cycle, or the next?

MIPS pipeline cycles

1 Answers