MIPS Datapath Confusion

Question

Been learning about mips datapath and had a couple questions.

Why is there a writeback stage? -Thoughts: If it didn't add more latency or make the clock cycles longer it seems like you could move the mux in the writeback stage into the Mem stage and remove the Mem/Writeback buffer and get rid of the writeback stage entirely. Why is this not the case?
Confusion about branch prediction and stalls. -Thoughts: If an add instruction follows beq instruction into the pipline (beq in ID stage, add in fetch stage) but the branch is taken, how does the add instruction then become converted to a no-op? (What control signals are set, how?)
When are the inter-stage buffers updated? Thoughts: I think they are updated at the end of the clock cycle but have been unable to verify this. Also, I am trying to understand what exactly happens during a stall. When a stall is needed does the IF/ID inter-stage buffer get locked? If so how is this done? Does the instruction then read from the buffer to determine what instruction should be in the ID stage?

Thanks for any help

Here's a picture of the pipeline:

I think I can answer #2. The inst following a branch is in the "branch delay slot" and is always executed [before the branch--taken or not]. So, given: beq $6,$7,label, add $8,$9,$7, sub $3,$4,$2, label: mul. The execution order is either add, beq, sub, mul for not-taken, or add, beq, mul for branch taken. The notion is that the add had to be pre-fetched by the inst fetch unit [because it runs "one ahead"], so why "waste" it? — Craig Estey

Isuru H Isuru H · Accepted Answer · 2016-11-04T09:47:40

Writeback stage is for writing the result back to registers. MEM/WB buffer is there to hold any data from the previous stage. By getting rid of the writeback stage, what you'll be doing is essentially extending the mem stage. For example in an instruction like, LW R1, 8(R2) contents of the memory location addressed by 8(R2) will be stored in the MEM/WB buffer. By copying the contents to the buffer, MEM stage can now accept another LW instruction, hence more ILP.
@Craig Estey have answered correctly for this. However even if you dont't do the swapping @Craig has mentioned, you can always use control signals and flush things if IF, ID stages for the following instructions.
I am not sure there is a precise answer as to when an inter stage buffer is updated. The way I see it is, at the beginning of a clock cycle, data in the inter stage buffer is not relevant and at the end of a clock cycle it is relevant. Control signals are being used to control whats is happening in each stage of the pipeline, meaning they can be used to tell IF stage not to fetch any.