Organizing pipeline in MIPS

Question

I'm unsure about how the following properties affect pipeline execution for a 5 stage MIPS design (IF, ID, EX, MEM, WB). I just need some clearing up.

• only 1 memory port
• no data fowarding.
• Branch stalls until end of * stage

Does the 1 memory port mean we cannot fetch or write when we read/write to mem (i.e. MEM stage on lw,sw you can't enter IF or another MEM)? With no forwarding does this means an instruction won't enter the ID stage until after or on the WB stage for the previous instruction it depends on? Idk what the branch stall means

Answer 1

A common assumption is that you can write in the first half of a cycle, and read in the second half of a cycle.

Lets say than I1 is your first instruction and I2 your second instruction, and I2 is using a register that I1 is modifying.

• Only 1 memory port. This means that you cannot read or write memory at the same time in two different stages of the pipelines. For instance, if I1 is at the MEM stage, another instruction cannot be at the IF stage at the same time, because both require memory access.

• No data forwarding. Data forwarding reflects to the fact that at the end of EX stage for I1, you forward the data to the ID cycle of I2. Consequently, no forwarding means that the pipeline has to wait for the WB stage of the I1 to go to ID stage of I2. With the asumption, you can go to ID stage at the same time as the WB stage of the previous instruction, because WB will write to memory during the first half of the cycle, and ID will read from memory during the second half of the cycle.

• Branch stalls until end of EX stage. This is a common asumption, that doesn't use branch prediction techniques. It simply states that an instruction after a branch has to wait until the end of EX stage to start ID stage. Recall that the address of the next instruction to be executed is known only at the EX stage of the branch instruction.

Answer 2

Comment: IF and MEM access separate sections of memory. One is data memory (.data) and the other instruction memory (.code or .text). It is designed this way so that accessing memory during IF and MEM does not cause a structural stall. The area which is used by .data is that used by the stack, with the stack is traditionally placed right at the "end" of the .data sector. This is why if you don't subtract from the stack pointer address before saving data to the stack you run the risk of overwriting your program code. As MIPS allows you to designate the stack address manually, some people choose put the stack a bit "before" the end in order to avoid problems if they know they will have space and not overwrite variables in MEM. For instance, placing the stack at 0x300 instead of 0x400 in WinMIPS64. I am not sure if that is good practice or not. But I have heard of people doing it.