Stalling or bubble in MIPS

Question

How many stalls do I need to execute the following instructions properly. I am a little confused with what I did, so I am here to see experts answers.

lw $1,0($2);

beq $1,$2,Label;

Note that the check whether the branch will occur or not will be done in decoding stage. But the source register rs of beq which is $1 in this case will be updated after writeback stage of lw instruction. So do we need to forward new data from Memory in memory stage to Decoding stage of beq instruction.

Here is the data path diagram:

Answer 1

The value that is fetched from the memory, is written to the register file in the write-back stage of the pipeline. Writes to the register file happen in the first half of the clock cycle, while reads from the register file happen in the second half of the clock cycle.

The value that is written to the register file can thus be read in the same clock cycle as it is written to the register file. Thus forwarding is not effective here.

As for the number of stalls needed, you need to insert two bubbles into the pipeline, as the lw instruction should be in the write back stage when the beq instruction is in the decode stage.

I hope this answers your question.