PIPELINE - mem(memory) and if(instruction fetch)

Question

In PIPELINE, MEM (memory) and IF (instruction fetch) are the same hardware element?

If are the same memory then 2 instructions can't load or store in the same cycle clock, I'm right?

MIPS processor diagram

Answer 1

MEM (memory) and IF (instruction fetch) are the same hardware element?

No, there are not, because a) why would they then be drawn as separate blocks, and b) code loads (== fetches) are not the same as data loads. Code fetches are used to understand what a new instruction wants to do with data — the function, and loads/stores are acts of obtaining arguments of that function.

If are the same memory then 2 instructions can't load or store in the same cycle clock, I'm right?

Both load and store are done inside MEM, not IF, stage. Because there is only one MEM block on the diagram, at most one memory-related operation can be done at each clock. This does not mean that the IF stage is necessarily blocked by MEM. Whether instruction/data memories are separate, or there is an instruction cache, would define, but it is outside the scope of the diagram you showed.