Maximum clock delay Xilinx ISE

Question

My design uses an Xilinx FPGA.

The synthesis report shows the following results:

Timing Summary:
---------------
Speed Grade: -3
   Minimum period: No path found
   Minimum input arrival time before clock: 1.903ns
   Maximum output required time after clock: 150.906ns
   Maximum combinational path delay: 97.819ns

I do not know if I should use 150.906 ns or 97.819 ns to calculate throught.

What is maximum clock delay?

Is your design a sequential design? Have you specified a clock signal? — Paebbels
My design is Full loop unrolling architecture. I wan to calculate maximum delay clock which is used to calculate throught. Thanks — MrFPGA

Martin Zabel Martin Zabel · Accepted Answer · 2015-11-10T09:27:00

I havn't heard the term 'throught' with respect to circuit timing anytime before, but maybe my explanantion will give you the right hint.

At first, the maximum clock delay can be found in the Static Timing Report after Place & Route. But, this figure is mostly meaningless because one must also take the maximum data delay from any input or to any output into account. The result is already provided by the synthesis report. Please note, that this report only provides estimated results. Real results are only available from the Static Timing Report.

If you look for the maximum clock frequency (the inverse of the minimum clock period), then your synthesis report states, that your design does not include a path from one FF to another driven by the same clock ("Minimum period: No path found").

If you want to synchronously communicate with another IC on your PCB then the other 3 numbers are relevant. For example, the line "maximum output required time after clock" states that, all output signals are valid 151 ns after the clock signal toggles at the input pin (rising or falling edge depending on your design). If any of this outputs drive the inputs of another IC and if this IC is driven by the same clock source, then you must add the "minimum input arrival time" of this second IC (found in its data sheet). If this time is for example 49 ns then, the minimum period of your shared clock would be (your) 151 ns + 49 ns = 200 ns, that would be 5 MHz.

Same applies for the "minimum input arrival time before clock" of your FPGA design which must be added to the "maximum output required time" of the driving IC. If this time is for example 31 ns, then the minimum period of your shared clock would be 31 ns + (your) 2 ns = 33 ns, that would be 30 MHz.

In the same way, the "maximum combinational path delay" must be added to the "maximum output required time" of the IC which drives your inputs plus the "minimum input arrival time" of the IC your FPGA is driving. Given the same example figures from above, then the minimum period of your shared clock would be 31 ns + (your) 98 ns + 49 ns = 178 ns, that would be 5.6 MHz.

More details are explained in Xilinx Timing Constraint User Guide. Above, I explained the System Synchronous mode.

A more compact representation for Xilinx Vivado is given in Vivado Design Suite User Guide - Using Constraints.

There was also this presentation earlier available on the internet, but I didn't find the source PDF anymore.

Maximum clock delay Xilinx ISE

1 Answers