8-bit Adder Error: The logic does not match a known FF or Latch template

Question

As far as I can understand that the hardware required to implement the code below is not supported in Xilinx ISE Web Pack. I'm trying to implement only the functionality of the 8-bit adder using an always block. Here's the code:

module Addr_8bit(Clk, Rst, En, LEDOut  
    );

     input Clk;
     input Rst;
     input En;
     output reg [7:0] LEDOut;

    always @(posedge Clk or posedge Rst) begin
            if(Rst)
                LEDOut <= 8'b00000000;
            if(En)
                LEDOut <= LEDOut + 8'b00000001;
    end
endmodule

The error is on the line where the non-blocking assignment: LEDOut <= LEDOut + 8'b00000001; is located.

Particularly it says that:

ERROR:Xst:899 - "Addr_8bit.v" line 33: The logic for <LEDOut> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

I am trying to make the LEDOut's 8-bit output to correspond to the each single one of 8 LEDs on the BASYS2 FPGA Board(Spartan-3E).

Thank You.

@Greg It can't be added. Because it is an enable signal which has to be separate from reset signal. It enables the addition LEDs to turn on. — Burak.
The else should be there. Reset (synchronous or asynchronous) must have priority. As currently written if Rst goes high at the rising edge of the clock with En high, then if(En) with take priority which is wrong and does not map to any flop in a library. Reversing the order of the if-statements may give the correct functional behavior but is against common best practices and may not synthesize correctly. — Greg
+1 for @Greg, if you have a reset, you really want to do nothing else than to handle it, with your code, both "if" conditions may occurs at the same time... — Mikitori
You have a counter example on the wikipedia page of Verilog: wikiwand.com/en/Verilog#/Example — Mikitori

apabst apabst · Accepted Answer · 2018-02-27T07:14:40

Change your behavioral description (the code inside the always block) as follows:

always@(posedge CLK or negedge RST) begin
    if(!RST) begin // Reset condition goes here
        LEDOut <= 0;
    end
    else begin // Everything else goes here
        if(En)
            LEDOut <= LEDOut + 1'b1;
    end
end

The reason your code won't synthesize is because you generally can't assign to the same register under the same edge of two different signals. (You can't have your always block trigger on the low to high transition of CLK and RST if you're assigning to a variable in both cases.) So you can't trigger the reset condition on the positive edge of RST, but you can do it on the negative edge. This is due to the way the physical register elements (called flip-flops) are designed.

8-bit Adder Error: The logic does not match a known FF or Latch template

1 Answers