Verilog LED bargraph issue/warnings

1
votes

First I am nearly brand new to verilog and how ise webpack works. So i am trying to write a bit of code the will accept an input square-wave into pin B2 on the basys2 fpga board. The issue i am having is that when i generate the program file (.bit) and load it onto the board all the LEDs are staying on. i do not receive any errors during the file formation and i understand the code to be correct for what i want it to do. i am receiving warnings about ff/latch trimming, and "the signal and is incomplete. the signal does not drive any load" . i have posted the code here as well as the ucf file

module IRVFILE(input clk, signal, 

                    output LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0 
                          );

parameter tenth= 5000000; // tenth of a second

reg[24:0]count;                //0-24bts

reg[24:0]displaycount;

reg[24:0]timer;

reg [7:0] leddata;


assign LED7= leddata[7];

assign LED6= leddata[6];

assign LED5= leddata[5];

assign LED4= leddata[4];

assign LED3= leddata[3];

assign LED2= leddata[2];

assign LED1= leddata[1];

assign LED0= leddata[0];

//////////////////////////////////////////////////////////////////////////////////

initial begin

    count <=0;
    timer <=tenth;

     displaycount =0;
     leddata = 0;

end

always@(posedge clk) begin

if(timer>=1)begin
    if(signal==1)begin

        count = count + 1;

        end
    end 
else begin
    timer <= tenth;

    displaycount <=count;

    count =0;
     leddata <=0;

end

if (displaycount >= 20) begin
    leddata[0]<=1;
    end

if (displaycount >=30)begin
    leddata[1]<=1;
    end

if (displaycount >=40)begin
    leddata[2]<=1;
    end

if (displaycount >=50)begin
    leddata[3]<=1;
    end

if (displaycount >=60)begin
    leddata[4]<=1;
    end

if (displaycount >=70)begin
    leddata[5]<=1;
    end

if (displaycount >=80)begin
    leddata[6]<=1;
    end

if (displaycount >=90)begin
    leddata[7]<=1;
    end

end
endmodule


ucf:

# clock pins for Basys2 Board
#NET "mclk" LOC = "B8"; # Bank = 0, Signal name = MCLK
#NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK
#NET "mclk" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "uclk" CLOCK_DEDICATED_ROUTE = FALSE;

NET "clk" LOC = B8;

## Pin assignment for EppCtl
## Connected to Basys2 onBoard USB controller
#NET "EppAstb" LOC = "F2"; # Bank = 3
#NET "EppDstb" LOC = "F1"; # Bank = 3
#NET "EppWR"       LOC = "C2"; # Bank = 3

#NET "EppWait" LOC = "D2"; # Bank = 3
#NET "EppDB<0>" LOC = "N2"; # Bank = 2
#NET "EppDB<1>" LOC = "M2"; # Bank = 2
#NET "EppDB<2>" LOC = "M1"; # Bank = 3
#NET "EppDB<3>" LOC = "L1"; # Bank = 3
#NET "EppDB<4>" LOC = "L2"; # Bank = 3
#NET "EppDB<5>" LOC = "H2"; # Bank = 3
#NET "EppDB<6>" LOC = "H1"; # Bank = 3
#NET "EppDB<7>" LOC = "H3"; # Bank = 3


# Pin assignment for DispCtl
# Connected to Basys2 onBoard 7seg display
#NET "segments<0>" LOC = "L14"; # Bank = 1, Signal name = CA
#NET "segments<1>" LOC = "H12"; # Bank = 1, Signal name = CB
#NET "segments<2>" LOC = "N14"; # Bank = 1, Signal name = CC
#NET "segments<3>" LOC = "N11"; # Bank = 2, Signal name = CD
#NET "segments<4>" LOC = "P12"; # Bank = 2, Signal name = CE
#NET "segments<5>" LOC = "L13"; # Bank = 1, Signal name = CF
#NET "segments<6>" LOC = "M12"; # Bank = 1, Signal name = CG
#NET "segments<0>" LOC = "N13"; # Bank = 1, Signal name = DP

#NET "digit<3>" LOC = "K14"; # Bank = 1, Signal name = AN3
#NET "digit<2>" LOC = "M13"; # Bank = 1, Signal name = AN2
#NET "digit<1>" LOC = "J12"; # Bank = 1, Signal name = AN1
#NET "digit<0>" LOC = "F12"; # Bank = 1, Signal name = AN0

# Pin assignment for LEDs

NET "LED0" LOC = "m5" ; # Bank = 3, Signal name = LD7

NET "LED1" LOC = "m11" ; # Bank = 2, Signal name = LD6

NET "LED2" LOC = "p7" ;  # Bank = 2, Signal name = LD5

NET "LED3" LOC = "p6" ;  # Bank = 2, Signal name = LD4

NET "LED4" LOC = "n5" ; # Bank = 2, Signal name = LD3

NET "LED5" LOC = "n4" ; # Bank = 3, Signal name = LD2

NET "LED6" LOC = "p4" ; # Bank = 2, Signal name = LD1

NET "LED7" LOC = "g1" ;  # Bank = 2, Signal name = LD0

# Pin assignment for SWs
#NET "swF" LOC = "N3";  # Bank = 2, Signal name = SW7
#NET "sw<6>" LOC = "E2";  # Bank = 3, Signal name = SW6
#NET "sw<5>" LOC = "F3";  # Bank = 3, Signal name = SW5
#NET "sw<4>" LOC = "G3";  # Bank = 3, Signal name = SW4
#NET "sw<3>" LOC = "B4";  # Bank = 3, Signal name = SW3
#NET "sw<2>" LOC = "K3";  # Bank = 3, Signal name = SW2
#NET "sw<1>" LOC = "L3";  # Bank = 3, Signal name = SW1
#NET "sw<0>" LOC = "P11";  # Bank = 2, Signal name = SW0

#NET "PB_F" LOC = "A7";  # Bank = 1, Signal name = BTN3
#NET "push" LOC = "M4";  # Bank = 0, Signal name = BTN2
#NET "btn<1>" LOC = "C11"; # Bank = 2, Signal name = BTN1
#NET "btn<0>" LOC = "G12"; # Bank = 0, Signal name = BTN0
#NET "line1" LOC = "B9";
#NET "line2" LOC = "C10";
#NET "line3" LOC = "A3";
#NET "line4" LOC = "B5";
#NET "signal" CLOCK_DEDICATED_ROUTE = FALSE;

## Loop back/demo signals
## Pin assignment for PS2
#NET "PS2C"    LOC = "B1"   | DRIVE = 2  | PULLUP ; # Bank = 3, Signal name = PS2C
#NET "PS2D"    LOC = "C3"   | DRIVE = 2  | PULLUP ; # Bank = 3, Signal name = PS2D

# Pin assignment for VGA
#NET "HS"   LOC = "J14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = HSYNC
#NET "VS"   LOC = "K13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = VSYNC

#NET "OutRed<2>"  LOC = "F13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED2
#NET "OutRed<1>"  LOC = "D13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED1
#NET "OutRed<0>"  LOC = "C14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = RED0
#NET "OutGreen<2>"  LOC = "G14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN2
#NET "OutGreen<1>"  LOC = "G13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN1
#NET "OutGreen<0>"  LOC = "F14"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = GRN0
#NET "OutBlue<2>"  LOC = "J13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = BLU2
#NET "OutBlue<1>"  LOC = "H13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = BLU1

## Loop Back only tested signals
//  | PULLDOWN ; # Bank = 1, Signal name = JA1

NET "signal" LOC = B2;

#NET "two" LOC = C5;

##NET "two" DRIVE = 2;
// | PULLDOWN ; # Bank = 1, Signal name = JA2
#NET "three" LOC = B5;
#NET "four" LOC = J3;
#NET "enA" LOC = A3;
#NET "three" DRIVE = 2;
#NET "enB" LOC = B6;#  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA3
#NET "PIO<75>" LOC = "B5"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JA4
#
//  | PULLDOWN ; # Bank = 1, Signal name = JB1

#NET "four" DRIVE = 2;
//  | PULLDOWN ; # Bank = 1, Signal name = JB2

#NET "one" DRIVE = 2;
#NET "PIO<78>" LOC = "C5"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB3
#NET "PIO<79>" LOC = "B7"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JB4
#
#NET "phone" LOC = C6; // | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC1
#NET "phtwo" LOC = B2; // | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JC4
#
#NET "stall" LOC = B9; //  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JD1
#NET "stallB" LOC = A9; //  | DRIVE = 2  | PULLUP ; # Bank = 2, Signal name = JD2
#NET "PIO<86>" LOC = "C13"  | DRIVE = 2  | PULLUP ; # Bank = 1, Signal name = JD3
#NET "cmp[0]" LOC = D12; //  | DRIVE = 2  | PULLUP ; # Bank = 2, Signal name = JD4
#NET "cmp[1]" LOC = C13;
#NET "cmp[2]" LOC = A13;

#NET "fire" LOC = A10;
2
verilogfpgaxilinx

2 Answers

1
votes

what I am seeing in your code is that you are using an initial statement, which is not synthesizable, and I see that you want to use it as a reset (to set default values). I recommend you to delete it and use a reset in the always statement. I put an async reset to give you the control when do you want to reset your design, it can be sync reset also.

//Delete Initial block

initial begin

    count <=0;
    timer <=tenth;

     displaycount =0;
     leddata = 0;

end 

always@(posedge clk, posedge a_rst) begin //This is an async reset which 
  if (a_rst) begin
    count <= 0;
    timer <= tenth;
    displaycount <=0;
    leddata <= 0;
  end
 else begin
   //Put the rest of the code here
 end

Also I recommend you that when you describe clock triggered logic, use non blocking assignments, do not combine blocking and non blocking in the same always process.

For example in this line of code: count = count + 1; //Change it to non blocking (i.e count <= count + 1;)

I recommend you to read this paper about blocking and non blocking assignments.

http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

Let me know how it goes and if you need more help

1
votes

With the provided Verilog code, if(timer>=1) will always be true. Therefore the structure of the if statements will never update displaycount, which in turn prevents leddata form being updated. When synthesizing, all of your Verilog code is being optimized out because no changes to a register can occur.

The Verilog needs to be re-coded. Run the Verilog in a simulator (pick a simulator http://en.wikipedia.org/wiki/List_of_Verilog_simulators or try http://www.edaplayground.com/home). Try running the code in FPGA after it works in simulation.

Best guess the desired result would look more like the follow: (http://www.edaplayground.com/s/6/189)

always@(posedge clk or negedge rst_n) begin : dff
    if( !rst_n ) begin : reset
        counting <= 1'b0;
        count    <= 25'b0;
        leddata  <= 8'b0;
    end : reset
    else begin
        counting <= signal;
        count    <= signal ? (count+1'b1) : 25'b0;
        leddata  <= next_leddata;
     end
end : dff

always @* begin : calc_leddata
    if ( !counting || signal ) begin : keep
        next_leddata = leddata;
    end : keep
    else begin : calc_new
        next_leddata = 8'b0;
        if (count >=20) next_leddata[0] = 1'b1;
        if (count >=30) next_leddata[1] = 1'b1;
        if (count >=40) next_leddata[2] = 1'b1;
        if (count >=50) next_leddata[3] = 1'b1;
        if (count >=60) next_leddata[4] = 1'b1;
        if (count >=70) next_leddata[5] = 1'b1;
        if (count >=80) next_leddata[6] = 1'b1;
        if (count >=90) next_leddata[7] = 1'b1;
    end : calc_new
end : calc_leddata