replace Block ROM IP in Xilinx ( Language: Verilog)

Question

I am using a Block ROM IP( in Xilinx) to store values and then processing them by fetching and processing as per requirement. Now I want to use the same values through test bench so that these stored values in ROM won't show up in resource utilization. In short, I wish to give input through test bench and read values one by one just as the way I was doing by changing address and fetching pixels.

FritzDC FritzDC · Accepted Answer · 2017-04-26T10:06:31

Put the BlockRom inside translate pragmas :

//synthesis translate_off
    // The comments in off and on are needed.
    // Place our simulation block here (not in comments).
//synthesis translate_on

The code between off and on will literally be removed from the eyes of the synthesis (and subsequent) tools.

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replace Block ROM IP in Xilinx ( Language: Verilog)

1 Answers