MIPS RAW stall on ID

1
votes

Ok, question regarding MIPs, forwarding is disabled. If there are two instructions that represent a RAW hazard, what is actually taking place?

Instruction 1 begins it's journey thru the pipeline. Instruction 2 is fetched, decoded, and the hazard is identified. The ID cannot read the data from the required registers, until the data is written back to the register file.

I believe that the ID starts and because of the hazard, the instruction stalls (as appropriately named) and the ID completes concurrently with the WB of instruction 1 as identified here:

INST 1 | IF | ID | EX | MEM | WB

INST 2 | -- | IF | ID | -----> | ID FINISH | EX | MEM | WB

So I was talking with a person who told me that it would be as follows:

IF-ID-EX-MEM-WB

_________IF-ID-EX-MEM-WB

(ID aligns with WB)

The implication was that when decoded it sees that the data isn't ready so it is nop'ed, and the same instruction is fetched again. There really was no answer about what happens to the PC since it had already retrieved instruction 3 (not quite sure how the pipeline would back up)

It makes more sense to me to disable/enable the clock to certain stages since that would seem to keep the instruction in the phase and prevent it from executing.

I can find some various academic material but nothing formal regarding the actual behavior.

1
mips

1 Answers

2
votes

There is no good answer to your question here. What you are asking about is micro-architecture, which involves decisions of how to implement a given ISA and could vary wildly from computer to computer.

In fact, both have been implemented, with the second approach being probably more likely today. Consider a super-scalar machine where there are multiple pipelines, say 4, that execute in parallel -- in this case instructions may wait in the window of the appropriate functional unit until there operands are calculated, which more closely resembles the second scenario you have presented.