why would this two mips instructions cause data hazards in pipeline?

Question

I am learning the pipeline in mips and was told tha this two instruction:

jal addr;
store $ra;store the value of $ra into memory

would cause data hazards, but I don't understand why.Could anybody help me ?

Answer 1

I don't know what store is, but all normal branch and jump instructions on MIPS are executed together with the immediately following instruction. In most trivial cases you may think that the branch/jump is executed the last and that other instruction, the first.

However, I'd not be surprised if the paired instructions execute internally pretty much as one indivisible instruction instead of two separate ones.

The potential problem here is that jal stores in $ra the address of the instruction that follows store. If store, or whatever instruction it is, uses $ra, there may be a race condition, data hazard, whatever you call it, between the two accesses to $ra and the end result may not be determinate or what one might naïvely expect.

Answer 2

The instruction in a MIPS branch delay slot is always fully executed before the branch is executed. So the store $ra instruction will store the value of $ra that existed before the jal instruction updates $ra. In other words this sequence:

    li  $ra, 0x1234
 L: jal addr
    nop
    store $ra, mem    # mem <- L + 8

will store a different value into memory than this sequence will:

    li  $ra, 0x1234
    jal addr
    store $ra, mem    # mem <- 0x1234

This is not an undefined sequence in the MIPS architecture, so the result is predictable.

The MIPS assembler will normally insert a nop after the jal unless noreorder is set.