What is an "interlocked pipeline" as in the MIPS acronym?

Question

I am going through a MIPS procesor architecture.

As per this tutorial it states : Microprocessor without Interlocked Pipeline Stages http://en.wikipedia.org/wiki/MIPS_architecture

One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline.
One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream.
Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the clock speed.
A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

This link says :--- https://www.cs.tcd.ie/Jeremy.Jones/vivio/dlx/dlxtutorial.htm

issue a "stall" instruction instead of a nop instruction upon a stall

What exactly is Interlock Pipeline disadvantage ?
Why routers use to prefer Processors with MIPS Architecture ?

Answer 1

A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

But in later version of MIPS, http://cs.nyu.edu/courses/spring02/V22.0480-002/vliw.pdf slide 9, interlocking was reintroduced into architecure:

• After all MIPS originally stood for something like Microprocessor without interlocking pipeline stages
• Because new implementations (with different memory latencies) would have required more than one slot and we don’t like correctness of code being dependent on the version of the implementation.
• Because other instructions required interlocking anyway (e.g. floating-point)
• Because it is not that painful to do interlocking

So, considering your questions:

What exactly is Interlock Pipeline disadvantage ?

Interlocking needs more complex hardware (control unit of CPU), which was not so easy to design and test in the era of hand-drawn transistors and CPUs of 100s thousands of transistors. They selected the goal of designing CPU core without Interlocking, but they failed. They were unable to produce compatible series of commercial chips without Interlocking.

Why routers use to prefer Processors with MIPS Architecture ?

Historically they were popular in first network devices and were used in next devices possibly due to inertia and investments in MIPS-based devices (both from the network device makers and from MIPS chip makers).

Check this book "See MIPS Run" By Dominic Sweetman, pages 15,16,22 http://books.google.com/books?id=kk8G2gK4Tw8C&pg=PR15

There were several easy accessible MIPS chips in the middle of 1990s, R4600, RM5200 and RM7000. The R4600 from 1993 was used by Cisco, next models had 64-bit bus and large on-chip L2 cache. They had enough performance to drive routers of the time.

In 2010s, I think, there are routers on ARM (there is a lot of SoCs with network and ARM now). This is because ARM is most widely licensed architecture (in terms of licensed core count, 78% in 2011); second architecture is ARC with 10% (check the Intel vPro sticker on your PC or laptop - if you has sticker, you has ARC core in your chipset; they are also used in many SSD controllers). MIPS is only third in this rating with only 6% of 10 billion cores total in market.