Verilog while error

Question

I have a school project in Verilog and I am very newbie at it. A part of the program is this

    integer x;
    assign x=1;
    **LINE 49** while(x<=9)
            begin
                assign lastBitsofP=P[1:0];
                if(lastBitsofP == 2'b00 || lastBitsofP ==2'b11)
                    begin
                    rightShift r1(shiftedValue,P);
                    end
                x=x+1;
            end

but I always get this error : "mainModule.v" line 49 expecting 'endmodule', found 'while' ,

The assign statement in verilog means continuously assign this value to this wire. So when you write assign x = 1 that means x is always equal to 1. — dave
ok. i changed that . now i get an error when I try to instantiate rightShift r1(shiftedValue,P) .. it says unexpected toke r1.. do you have any ideea ? — Cosmin Grigore

dave dave · Accepted Answer · 2012-11-08T23:03:40

You need to stop coding and think about what is going on. You are modelling hardware and connections. When you write assign x = that means "I have a wire and I want you to drive that wire with this value". If you have a module like r1 that you want connected it must be connected always you can't go "oh wait, if this happens just create a multiply unit for me".

You need to instantiate your connections at the start. If you only want the right shifted value sometimes then you can have a statement like assign out = select ? shiftedValue : unshiftedValue; And then you just need to write the logic for select.

And you'll probably want a flip-flop for your output. Something like

reg [31:0] result;
always @(posedge clk)
begin
    result <= out;
end

Verilog while error

1 Answers