verilog syntax error with always block

Question

I am new to verilog.I dont know what the hell is wrong with my code.The program displays the counter value at the given moment from 0H to 16H. key[2] is the button that will increment the counter, and sw[0] resets the counter.

else if(sw[9:5]==5'b00100)
begin
    counter = 0;
    hex2 = 7'b1000000;
    always@(negedge sw[0],posedge key[2])
    begin
        if(~sw[0]) counter = 0;
        else if(key[2])begin
            if(counter == 16'hFFFF) counter = 0;
            else                    counter = counter +1;
        end
    end
end

The error I get says Verilog HDL syntax near text "always"; expecting ";", or "@", or "end" or an identifier("always" is a reserved keyword), or a system task, or "{", or a sequential statement.

my counter = 0; is defined at the top outside my upper most module as integer counter;

Your help is greatly appreciated.

akshayj akshayj · Accepted Answer · 2014-05-06T06:34:41

always block is not allowed in sequentially executed if..else block.

One way you can try is : @(negedge sw[0],posedge key[2])

This will trigger on any change in above two signals, but it will detect only one change.

Looks like you want to enable the counter when sw[9:5]==5'b00100 Why not try setting a flag here, and then use an always @flag block to implement the running counter.

verilog syntax error with always block

1 Answers