Verilog instantiate issue?

Question

I'm having a strange issue where my instantiates will not work in this verilog code. After having created the megafunction in altera's wizard, I'm trying to instantiate it using the template given in the .inst file. I have the .v file for the megafunction included in the project, and have set the data ins and outs to their proper variables for my design. But I cannot get anything past this error "Error (10170): Verilog HDL syntax error at functionalblock.v(183) near text "("; expecting ";""

The else if is part of a much larger if, else if chain contained in an Always block.

else if (fs == 4'b0011) begin
if(instrsel == 2'b00) begin
    cns_mul_1   cns_mul_1_inst (
    .dataa ( TAout ),
    .datab ( TBout ),
    .result ( {aluout, aluouttr}  )
    ); 
end
else if(instrsel == 2'b01) begin
   cns_div_1    cns_div_1_inst (
    .denom ( TBout ),
    .numer ( TAout ),
    .quotient ( ALUout ),
    .remain ( aluouttr )
    ); 
end
else if(instrsel == 2'b10) begin
     cns_mul_1 cns_mul_1_inst (
    .dataa ( TAout ),
    .datab ( TBout ),
    .result ( {aluout, aluouttr}  )
    ); 
end
else if(instrsel == 2'b11) begin
    cns_div_1   cns_div_1_inst (
    .denom ( TBout ),
    .numer ( TAout ),
    .quotient ( ALUout ),
    .remain ( aluouttr )
    );
end 
end

Answer 1

You cannot instantiate modules inside a conditional block. When you instantiate a block you are creating hardware that is always there. What you want is to instantiate all of the blocks you are going to need and then select the result you want with your if-else condition.

Read up on instantiating modules in section 23.3 of the standard