Instantiate Verilog module from parameter name

0
votes

I would like to write a Verilog module such that it can instantiate the module named in its parameter.

module parent();
  parameter MODULE = "missing_module";

  initial $display("I want to instantiate %s", MODULE);
endmodule

module top();
  parent #(.MODULE("child_1")) p();
endmodule

Except that instead of that $display, a module instantiation of child_1 as that was the name passed in via the MODULE parameter.

2
verilog

2 Answers

3
votes

This cannot be done in Verilog. If you know all the possible choices for MODULE, you could do agenerate-case

module parent();
  parameter MODULE = "missing_module";

  case(MODULE)
  "child_1": child_1 inst_name(ports);
  "child_2": child_2 inst_name(ports);
  "child_3": child_3 inst_name(ports);
 endcase
endmodule

Other options are using Verilog configs or text macros. But I would have to have more details about your situation.

2
votes

You cannot do it in verilog with parameters. If you really need to have arbitrary module names, you can do it with macros, something like the following:

`define PARENT_MODULE(CHILD_MODULE) \
    module parent();\
        CHILD_MODULE child();\
    endmodule

`PARENT_MODULE(my_child)

module top;
  parent p();
endmodule

 ....

`undef PARENT_MODULE