Error Number 10170 in Verilog using If/Else and Case Statements

0
votes

I am trying to compile the following code but whenever I do I get the errors:

'10170 Verilog HDL syntax error at FSM.v(9) near text "case"; expecting an operand'

'10170 Verilog HDL syntax error at FSM.v(9) near text ")"; epecting "<=" or "="'

'10170 Verilog HDL syntax error at FSM.v(11) near text "4"; expecting "end"'

module FSM (in0, in1, in2, in3, S, out0, out1, out2, out3); 
input in0, in1, in2, in3, S;
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
always @(in0 or in1 or in2 or in3 or S)
begin
    if(S == 0) begin
    {
        case({in3, in2, in1, in0})
            4'b0000: {out3, out2, out1, out0} = 4'b0000; //0->0
            4'b0001: {out3, out2, out1, out0} = 4'b0011; //1->3
            4'b0010: {out3, out2, out1, out0} = 4'b0110; //2->6
            4'b0011: {out3, out2, out1, out0} = 4'b1001; //3->9
            4'b0100: {out3, out2, out1, out0} = 4'b0010; //4->2
            4'b0101: {out3, out2, out1, out0} = 4'b0101; //5->5
            4'b0110: {out3, out2, out1, out0} = 4'b1000; //6->8
            4'b0111: {out3, out2, out1, out0} = 4'b0001; //7->1
            4'b1000: {out3, out2, out1, out0} = 4'b0100; //8->4
            4'b1001: {out3, out2, out1, out0} = 4'b0111; //9->7
        endcase
    }
    end
    else begin
    {
        case({in3, in2, in1, in0})
            4'b0000: {out3, out2, out1, out0} = 4'b0111; //0->7
            4'b0001: {out3, out2, out1, out0} = 4'b1000; //1->8
            4'b0010: {out3, out2, out1, out0} = 4'b1001; //2->9
            4'b0011: {out3, out2, out1, out0} = 4'b0000; //3->0
            4'b0100: {out3, out2, out1, out0} = 4'b0001; //4->1
            4'b0101: {out3, out2, out1, out0} = 4'b0010; //5->2
            4'b0110: {out3, out2, out1, out0} = 4'b0011; //6->3
            4'b0111: {out3, out2, out1, out0} = 4'b0100; //7->4
            4'b1000: {out3, out2, out1, out0} = 4'b0101; //8->5
            4'b1001: {out3, out2, out1, out0} = 4'b0110; //9->6
        endcase
    }
    end
end
endmodule

with the last error repeating for every line of code that's found in the case statements. If anyone has an idea of what I have wrong and how I could fix this I'd greatly appreciate it!

2
verilog

2 Answers

3
votes

Remove the curly braces ({..}) after if condition. Verilog is not C which requires curly braces, in Verilog, we use begin..end for multi-line procedural statements.

Also, the use of always @(*) (or always_comb in SystemVerilog) is recommended for automatic sensitivity, instead of manual sensitivity of always @(in0 or in1 or in2 or in3 or S).

You might have to go through detailed Verilog syntax. Refer Begin..end link and always sensitivity question for some of the information. Refer IEEE 1364-2001 for Verilog and IEEE 1800-2012 for SystemVerilog.

0
votes

I believe that you cannot use a concatenation operation as the argument for a case statement or on the left hand side of an assignment.

So you will need to do something like this:

....
reg [3:0] inword, outword;
begin
   inword = {in3, in2, in1, in0};
   if(S == 0) begin
      case (inword)
         4'b0000: outword = 4'b0000; //0->0
         ...
      endcase
   ...
   end
   out3 = outword[3];
   out2 = outword[2];
   out1 = outword[1];
   out0 = outword[0];      
end;