errors in modelsim verilog compile

Question

I'm designing a 8 bit sequence detector. But following code gives me error while compiling in modelsim

-- Compiling module SEQDET ** Error: F:\Modeltech_pe_edu_10.4a\examples\avlsihw5.v(30): A begin/end block was found with an empty body. This is permitted in SystemVerilog, but not permitted in Verilog. Please look for any stray semicolons. ** Error: (vlog-13069) ** while parsing macro expansion: 'A' starting at F:\Modeltech_pe_edu_10.4a\examples\avlsihw5.v(43) ** at F:\Modeltech_pe_edu_10.4a\examples\avlsihw5.v(43): near ";": syntax error, unexpected ';', expecting ':'.

** Error: F:\Modeltech_pe_edu_10.4a\examples\avlsihw5.v(46): (vlog-13205) Syntax error found in the scope following 'shiftReg'. Is there a missing '::'?

Verilog code:

module seq_det;
    wire SEQ_DETECTED;
    reg [0:7] latch;
    wire RST_N, SCK;
    reg SCK,SDI;
SEQDET s1(SEQ_DETECTED,latch,RST_N,SDI,SCK);
clkGen #(10) cg(SCK);
//TEST at(latch,RST_N,SDI,SEQ_DETECTED,SCK);
endmodule

module SEQDET(.SEQ_DETECTED(SEQ_DETECTED),.latch(PATTERN),.RST_N(RST_N),.SDI(SDI),.SCK(SCK));
    `define A 3'b000;
    `define B 3'b001;
    `define C 3'b100;
    reg [7:0] shiftReg;
    output SEQ_DETECTED;
    input PATTERN;
    input RST_N, SDI, SCK;
    wire SEQ_DETECTED;
    reg [2:0] state;
    reg RST_N, SDI;
    integer count, match;

    initial begin
        match = 0;
        count = 0;
        shiftReg = 8'b00000000;
        RST_N = 1;
        SEQ_DETECTED = 0;
        state = `A;
    end

    always @(negedge RST_N) begin
        PATTERN = {8{1'b0}};
        SEQ_DETECTED = 0;
        count = 0;
        match = 0;
    end

    always @(posedge SCK)
       if ( SCK && RST_N)
            case (state)
       `A : //begin
            while(count <= 8) begin
               shiftReg <= shiftReg | SDI ;
               shiftReg = shiftReg >> 1;
               count = count + 1;
               if(count === 8)
                   if(shiftReg === PATTERN)
                         match = 1;            
                   else
                         match = 0;
               else ; end
            state <= match ? `B : `C ;
            //end
      `B : //begin
           count = 0;
           match = 0;
           shiftReg = {8{1'b0}};
           SEQ_DETECTED = 1;
           #20 SEQ_DETECTED = 0;
           state <= `A ;
           //end
      `C : //begin
           count = 0;
           match = 0;
           shiftReg = {8{1'b0}};
           state <= `A ;
           //end
 endcase
 endmodule

module clkGen(SCK);
    output SCK;
    parameter period = 10;
    reg SCK;
    initial SCK = 0;
    always
        #(period/2) SCK = ~SCK;
endmodule

Answer 1

Errors,
1. You can not declare two varible with same name, i.e. wire and reg CLK.
2. No need to bind or connect instantiated module, i.e. module SEQDET(.SEQ_DETECTED(SEQ_DETECTED),.latch(PATTERN),.RST_N(RST_N),.SDI(SDI),.SCK(SCK));
3. connected module is connected by wire so you can not connect with reg, it should be i.e. input wire RST_N, SDI, SCK; only
4. in case statement, syntax error like, else ; end, it should be

      if(count === 8)
           if(shiftReg === PATTERN)
                 match = 1;            
           else
                 match = 0;
       else
    end
    state <= match ? B : C ;

5. etc, please remove compilation errors, check for <= and = usage in always blocks

Answer 2

Then error you are getting is likely related to the semicolon after the `define statements. `define as literal substitutions. When you say

case (state)
  `A : begin // <-- appears legal syntax
    ...

you get :

case (state)
  3'b000; : begin // <-- illegal syntax
    ...

Change `define A 3'b000; to `define A 3'b000, then you will get the correct syntax.

You are doing the module header in an unusual way. A module whose ports are declared with .port_identifier(port_expression) is technically legal, but is rarely used in a header; it is commonly used when connecting nets to a module instance. Most people write there non-ANSI style module headers ports with only the port_expression, dropping the .port_identifier(). I recommend using a ANSI style header (unless you are required to follow strict 1995 coding style).

module SEQDET(.SEQ_DETECTED(SEQ_DETECTED),.latch(PATTERN),.RST_N(RST_N),.SDI(SDI),.SCK(SCK));
    `define A 3'b000; // <---do not use semicolons here
    `define B 3'b001; // <-+ here
    `define C 3'b100; // <-+ and here
    reg [7:0] shiftReg;
    output SEQ_DETECTED;
    input PATTERN; // <-- Are you sure you want this as a single bit?
    input RST_N, SDI, SCK;
    wire SEQ_DETECTED;
    reg [2:0] state;
    reg RST_N, SDI;
    integer count, match;

Would be better written as:

module SEQDET(
  output reg SEQ_DETECTED, // <-- based on ussage, this needs to be an reg type
  input [7:0] PATTERN, // <-- I'm guessing you meant 8-bits
  input RST_N, SDI,SCK
);
  `define A 3'b000
  `define B 3'b001
  `define C 3'b100
  reg [7:0] shiftReg;
  reg [2:0] state;
  integer count, match;

To be synthesizable always @(negedge RST_N) and always @(posedge SCK) need to be merged into one always @(posedge SCK or negedge RST_N)

It is highly recommended to use non-blocking assignments (<=) when assigning flops.

Delays (ex: #20) are not synthetically. You should create an extra state.