D Flip Flop in VHDL

Question

I'm trying to implement a D Flip Flop in VHDL, using a D Latch I wrote. But there seems to be an error with the clock, and I can't figure out what that is.

Here is the code for my D Latch.

Library ieee;
Use ieee.std_logic_1164.all;

entity d_latch is
  port (c,d : in std_logic;
        q,nq : out std_logic);
end d_latch;

architecture arch of d_latch is

Signal qt, nqt: std_logic;

begin  

  qt <= (d nand c) nand nqt;
  nqt <= ((not d) nand c) nand qt;

  q <= qt;
  nq <= nqt;

end arch;

I tested it and it works, and here is the code for my d flip flop:

Library ieee;
Use ieee.std_logic_1164.all;

entity d_flipflop is
  port (d,clock : in std_logic;
        q,nq : out std_logic);
end d_flipflop;

architecture arch of d_flipflop is

Component d_latch
Port
(
  d, clk: in std_logic;
  q, nq : out std_logic 
);
End Component ;

Signal qt, nqt: std_logic;

begin  

dl1: d_latch port map (
  d => d,
  clk => not clock,
  q => qt
);

dl2: d_latch port map (
  d => qt,
  clk => clock,
  q => q,
  nq => nq
);

end arch;

and here is the error:

** Error: /home/devplayer/CSC343/Lab_2_Content/d_flipflop.vhd(25): (vcom-1436) Use of non globally static actual (prefix expression) of formal "clk" requires VHDL 2008.

Thank you

Charles Steinkuehler Charles Steinkuehler · Accepted Answer · 2012-02-15T02:03:06

You cannot use full expressions in port assignments. Instead of inverting the clock when assigning it to the port for your dl1 instance, create an inverted clock and use that:

clockn <= not clock;

dl1: d_latch port map (
  d => d,
  clk => clockn,
  q => qt
);

D Flip Flop in VHDL

1 Answers