VHDL Clock Test Bench

Question

I am trying to run a code that I have picked up online, but it somehow the testbench is failing to run the expected output on GHDL.

Architecture Code library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity clk200Hz is
    Port (
        clk_in : in  STD_LOGIC;
        reset  : in  STD_LOGIC;
        clk_out: out STD_LOGIC
    );
end clk200Hz;

architecture Behavioral of clk200Hz is
    signal temporal: STD_LOGIC;
    signal counter : integer range 0 to 124999 := 0;
begin
    frequency_divider: process (reset, clk_in) begin
        if (reset = '1') then
            temporal <= '0';
            counter <= 0;
        elsif rising_edge(clk_in) then
            if (counter = 124999) then
                temporal <= NOT(temporal);
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= temporal;
end Behavioral;

Test Bench:

  LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY clk200Hz_tb IS
    END clk200Hz_tb;

    ARCHITECTURE behavior OF clk200Hz_tb IS 
      COMPONENT clk200Hz
      PORT(
        clk_in : IN  std_logic;
        reset  : IN  std_logic;
        clk_out: OUT std_logic
      );
      END COMPONENT;

      -- Inputs
      signal clk_in  : std_logic := '0';
      signal reset   : std_logic := '0';
      -- Outputs
      signal clk_out : std_logic;
      constant clk_in_t : time := 20 ns; 
    BEGIN 
      -- Instance of unit under test.
      uut: clk200Hz PORT MAP (
        clk_in  => clk_in,
        reset   => reset,
        clk_out => clk_out
      );

      -- Clock definition.
      entrada_process :process
        begin
        clk_in <= '0';
        wait for clk_in_t / 2;
        clk_in <= '1';
        wait for clk_in_t / 2;
      end process;

      -- Processing.
      stimuli: process
      begin
        reset <= '1'; -- Initial conditions.
        wait for 100 ns;
        reset <= '0'; -- Down to work!
            wait;
      end process;
    END;

I expect a wave that would form a clock pulsing up and down, however that does not seem to be the case. I wonder what is wrong with the design.

I ran the following commands:

ghdl -s *.vhd
    ghdl -a *.vhd
    ghdl -e clk200Hz_tb
    ghdl -r clk200Hz_tb --vcd=led.vcd 
    gtkwave led.vcd

and this is my output enter image description here
but for clock out, I expect a up and down signal, not a signal of 0.

Thanks

The VHDL code seems right, what ghdl command are you using. How do you assert there is something wrong? — Jonathan Drolet

user288231 user288231 · Accepted Answer · 2015-05-24T04:22:36

I have fixed the problem, in my running command, I simply added ghdl -r clk200Hz_tb --vcd=led.vcd --stop-time=100ns.

VHDL Clock Test Bench

2 Answers