Can't run AND bank testbench?

Question

This is my code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY AND_Bank_Test IS
END AND_Bank_Test;

ARCHITECTURE behavior OF AND_Bank_Test IS 

 -- Component Declaration for the Unit Under Test (UUT)

COMPONENT AND_Bank
PORT(
        Input : IN  std_logic_vector(7 downto 0);
     AND_Bit : IN  std_logic;
        Output : OUT  std_logic_vector(7 downto 0)
    );
END COMPONENT;


   --Inputs

signal Input : std_logic_vector(7 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';

--Outputs

signal Output : std_logic_vector(7 downto 0);

-- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 


BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: AND_Bank PORT MAP (
      Input => Input,
      AND_Bit => AND_Bit,
      Output => Output
    );

   -- Stimulus process

   stim_proc: process
    begin       
-- hold reset state for 100 ns.

    wait for 100 ns;    

    Input <= "00000001" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "00111011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "10111011" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "10110011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "01110111" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "10110000" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "11110011" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "01110011" ; AND_Bit <= 1; 
    wait for 100 ns;    

    Input <= "10111111" ; AND_Bit <= 0; 
    wait for 100 ns;    

    Input <= "11111111" ; AND_Bit <= 1; 
    wait for 100 ns;    
wait;
end process;

END;

And this is the error I get:

Type std_logic does not match with the integer literal (this refers to Input <= "00000001" ; AND_Bit <= 0; )

I've replaced my code with this:

ENTITY AND_Bank_Test IS END AND_Bank_Test;

ARCHITECTURE behavior OF AND_Bank_Test IS

COMPONENT AND_Bank
PORT(
        Input : IN  std_logic_vector(15 downto 0);
     AND_Bit : IN  std_logic;
        Output : OUT  std_logic_vector(15 downto 0)
    );

END COMPONENT;

--Inputs

signal Input : std_logic_vector(15 downto 0) := (others => '0');
signal AND_Bit : std_logic := '0';

--Outputs

signal Output : std_logic_vector(15 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: AND_Bank PORT MAP (
      Input => Input,
      AND_Bit => AND_Bit,
      Output => Output
    );

-- Stimulus process

stim_proc: process begin
-- hold reset state for 100 ns.

    wait for 100 ns;    

    Input <= "0000000000000001" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000000111011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000010111011" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000010110011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000001110111" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000010110000" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000011110011" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000001110011" ; AND_Bit <= '1'; 
    wait for 100 ns;    

    Input <= "0000000010111111" ; AND_Bit <= '0'; 
    wait for 100 ns;    

    Input <= "0000000011111111" ; AND_Bit <= '1'; 
    wait for 100 ns;

wait; end process;

END;

is this the correct way to run a AND bank test? why can't run it with only 8 bits?

Josh Josh · Accepted Answer · 2014-04-13T13:52:29

You need to use a single quote, e.g.:

Input <= "00000001" ; AND_Bit <= '0';

If you are not using a single quote, it assumes you are assigning an integer value to AND_Bit, which is why it is giving you an error.

Can't run AND bank testbench?

2 Answers