Using a specify block to code a clock to output hold time?

Question

You can set a module path delay in a specify block as follows (in this case, the clock to q delay in a DFF):

specify
  specparam tPLHc = 4:6:9, tPHLc = 5:8:11;
  (clock *> q) = (tPLHc, tPHLc);
endspecify

In other words, the minimum delay for a 0->1 transition on q is 4 time units, and so on. However, this only gives the delays for a new valid output on q, and doesn't specify how long the previous q output holds after a clock edge (or the stability window over which the new q is valid). Assume, for example, that q remains valid for 2 time units after a clock rising edge, and takes on the new value after 4 time units.

Is there some way to specify the output hold time, or does this have to be manually coded?

dave_59 dave_59 · Accepted Answer · 2021-01-03T21:11:06

That information is built into the setup/hold requirements of the next stage. Realize that the min/max delays are statistical thresholds on a slope, and the true output slope depends in the input slopes. And those slopes depend on resistance/capacitance networks that you cannot normally get without analog analysis. So the hold times have to be pessimistic enough to give you practical worse case senarios.

Using a specify block to code a clock to output hold time?

1 Answers