How to create a pos-edge Write pulse into a neg-edge pulse?

Question

I have a data source signal that transitions high on the positive edge of its clock when it has data ready to be written.

I also have ram memory (running from the same clock) but expects it's write request signal to transition on the negative edge of the clock (and stay high until the following negative edge of the clock).

If I try driving the memory's wr_req directly from the data source then both the clock and wr_req transition at the same time and the memory doesn't get the data.

How can I delay the write pulse such that it goes high (for one cycle) starting on the next negative edge of the clock?

one of possible ways is to turn on write_en, wait for an acknowledgement from the writer, then turn off the write_en. — Serge

Charles Clayton Charles Clayton · Accepted Answer · 2017-12-01T00:43:19

If I understand correctly, this should do what you want:

reg blah;
always @(negedge clk) begin
    blah <= !foo;
end

Or even:

reg blah;
always @* begin
    if (!clk) begin
        blah = !foo;
    end
end

Simulated:

How to create a pos-edge Write pulse into a neg-edge pulse?

1 Answers