verilog code for serial data transfer on the same edge as as sync signal edge

Question

I am trying to code for serial communication, where I have a clock, a sync line WS and serial data line. I have to drive the data on the rising edge of the WS signal on positive of clk. Can you, please, guide me on this? I have been trying to do so but either I am getting a lock cycle delay or no toggle on the output line.

Answer 1

It seems like your explanation is incomplete because it contradicts itself.

If you have a clock, you're probably looking to flop your data. You can then use the signal ws to enable data taking on the next rising edge of said clock, and the corresponding data would be available at Q on the flops the next cycle.

However, if you want the data to be operated on that cycle, you shouldn't use a clock at all. Make the operations combinational, and when the data arrives it will begin processing immediately.