During simulation, why do flip-flops take the value preceding the transition while conditional(if) statements take the value after the transition?

Question

As you can see in the cursor below, the if statement looks AFTER the transition (it sees rst = 0 and thus sets a equal to in) rather than seeing rst = 1.

BUT it can also be seen that c takes the value of a BEFORE the transition.

I am wondering why this is. Suppose you want to gate a register with an enable that is delayed on clock cycle, then you can not use if (enable_delayed) because (ideally) the falling transition will happen on the rising edge of the clock and thus not be detected in simulation.

I have not had success finding my problem online. It is hard to explain and search for. Thanks for the help.

Code:

module project_test 
( input logic clk, rst, 
    input logic in,
    output logic a,
    output logic b,
    output logic c
);

always@(posedge clk) 
    if(rst) a <= 1'b0;
    else    a <= in;
always@(posedge clk) 
    if(a) b <= a;
always@(posedge clk) 
    c <= a;

endmodule: project_test

Tinkerer Tinkerer · Accepted Answer · 2021-07-27T05:18:12

My guess would be you are setting rst earlier than you think and it is already 0 when the logic inside the module observes the positive clk edge.

If you were to set rst to 0 as a result of a @(posedge clk) things would work as you expect, but I suspect rst is being changed in parallel with clk.

When debugging this sort of thing, I always try to delay the assignment of the values. That is, in your module here replace <= with <= #1 .

During simulation, why do flip-flops take the value preceding the transition while conditional(if) statements take the value after the transition?

1 Answers