Verilog self checking testbench will not run? Building a simple ALU, this shouldn't be so hard

Question

I am tasked with building an ALU. However, I must not understand how the testbench should run. I have run other simple testbenches just fine.

code compiles (using quartus)
made a text file and turned it into a "test.tv" file
opened modelsim and added file
when I run it, is has an issue with the y and zero ports.

Here is my code:

module ALU(input [31:0] a,b,
input [2:0] f,
output reg [31:0] y ,
output reg zero);

always @(*) begin

    case(f)
      3'b000: y = a & b;  
      3'b001: y = a | b;  
      3'b010: y = a + b;    
      3'b011: y = 32'b0;    
      3'b100: y = a & ~b;
      3'b101: y = a | ~b;
      3'b110: y = a - b;
      3'b111: y = a < b;
     default: y = 32'b0;
  endcase
if(y==0)
    zero=1'b1;
else
    zero=1'b0;
end 
endmodule

//**********************

module testALU();
 reg clk;
 reg [31:0]a, b, yexpected;
 reg [2:0]f;
 reg [31:0]y; 
 reg zeroexpected;
 reg zero;
 reg[31:0] vectornum, errors;
 reg [100:0] testvectors[10000:0];

 ALU dut(a,b,f,yexpected,zeroexpected);

always
begin
    clk = 1; #5; clk = 0; #5;
end

initial
begin
    $readmemb("test.tv", testvectors);
    vectornum = 0; errors = 0;
end

always @(posedge clk)
begin
#1; {a,b,f,yexpected,zeroexpected} = testvectors[vectornum];
end

always @(negedge clk)
begin
if (y !== yexpected) begin
$display("Error: inputs = %b", {a,b,f});
$display(" outputs = %b (%b expected)", y, yexpected);
errors = errors + 1;
end

vectornum = vectornum + 1;
if (testvectors[vectornum] === 100'bx) begin
    $display("%d tests completed with %d errors", vectorum, errors);
    $stop;
 end
 end
endmodule

//*************************************

ERROR:

** Error: **(vsim-3043) Unresolved reference to 'vectorum'. Time: 0 ps Iteration: 0 Instance: /testALU File: C:/Users/prest/Desktop/Hardware Design/ALU/testALU.v Line: 40

** Error ** (suppressible): (vsim-3053) Illegal output or inout port connection for port 'y'. Time: 0 ps Iteration: 0 Instance: /testALU/dut File: C:/Users/prest/Desktop/Hardware Design/ALU/testALU.v Line: 11

** Error **(suppressible): (vsim-3053) Illegal output or inout port connection for port 'zero'. Time: 0 ps Iteration: 0 Instance: /testALU/dut File: C:/Users/prest/Desktop/Hardware Design/ALU/testALU.v Line: 11

This is what my "test.tv" file looks like in binary

> 00000000000000000000000000000000_00000000000000000000000000000000_010_00000000000000000000000000000000_1
> 00000000000000000000000000000000_11111111111111111111111111111111_010_11111111111111111111111111111111_0
> 00000000000000000000000000000000_01010101010101010101010101010101_010_01010101010101010101010101010101_0

I know this might seem stupid and simple, but I am really trying to learn this and obviously do not understand something. Can someone please help?

toolic toolic · Accepted Answer · 2020-09-11T20:49:54

You have a few errors.

Change vectorum to vectornum.

Change your module instance connections so that there is no contention with the testbench signals for zeroexpected and yexpected.

Change the signals connected to the module outputs from reg to wire.

module testALU();
   reg clk;
   reg [31:0] a, b, yexpected;
   reg [2:0]  f;
   wire [31:0] y; 
   reg        zeroexpected;
   wire        zero;
   reg [31:0] vectornum, errors;
   reg [100:0] testvectors[10000:0];

   ALU dut(a,b,f,y,zero);

   always
     begin
        clk = 1; #5; clk = 0; #5;
     end

   initial
     begin
        $readmemb("test.tv", testvectors);
        vectornum = 0; errors = 0;
     end

   always @(posedge clk)
     begin
        #1; {a,b,f,yexpected,zeroexpected} = testvectors[vectornum];
     end

   always @(negedge clk)
     begin
        if (y !== yexpected) begin
           $display("Error: inputs = %b", {a,b,f});
           $display(" outputs = %b (%b expected)", y, yexpected);
           errors = errors + 1;
        end

        vectornum = vectornum + 1;
        if (testvectors[vectornum] === 100'bx) begin
           $display("%d tests completed with %d errors", vectornum, errors);
           $stop;
        end
     end
endmodule

This fixes all the compile errors.

Verilog self checking testbench will not run? Building a simple ALU, this shouldn't be so hard

1 Answers