Verilog sync counter

Question

module syncounter(qa,qabar,qb,qbbar,overflow,ja,ka,jb,kb,clk,rst);  
output qa,qabar,qb,qbbar,overflow;  
input ja,ka,jb,kb,clk,rst;  
reg qa,qb,qabar,qbbar,overflow;  
//var1 = qa;

jkflip jk1(qa,qabar,ja,ka,clk,rst);  
assign var1 = qa;  
jkflip jk2(qb,qbbar,var1,var1,clk,rst);  
always @ (ja,ka,jb,kb)  
begin  
if(qa & qb)   
begin  
overflow = 1;  
end  
end  
endmodule

The code for flip flop is

module jkflip(q,qbar,j,k,clk,rst);  
input j,k,clk,rst;  
output q,qbar;  
wire j,k,clk,rst;  
reg q,qbar;  
always @(posedge clk)  
begin  
if(rst) q<=~q;  
else   
begin  
case ({j,k})  
    2'b00 : q<=q;  
    2'b01 : q<=1'b0;  
    2'b10 : q<=1'b1;  
    2'b11 : q<=~q;  
endcase   
end  
end  
endmodule

Testbench for counter

module syncountw();

reg j0,k0,j1,k1,clk,rst;
wire q0,q0bar,q1,q1bar,overflow;
syncounter syn1(q0,q0bar,q1,q1bar,overflow,j0,k0,j1,k1,clk,rst);
always #1 clk = !clk;
//always #1 j0 =1 ;
//always #1 k0 = 1;
initial begin
clk = 1;
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;
#2
j0 = 1;
k0 = 1;

end
endmodule

I am getting a error called:

 Error (suppressible): (vsim-3053)   C:/Modeltech_pe_edu_10.4/examples/syncounter.v(7): Illegal output or inout port connection for port 'q'.  
#    Time: 0 ns  Iteration: 0  Instance: /syncountw/syn1/jk1 File:   C:/Modeltech_pe_edu_10.4/examples/jkflip.v  
# ** Error (suppressible): (vsim-3053)   C:/Modeltech_pe_edu_10.4/examples/syncounter.v(7): Illegal output or inout port    connection for port 'qbar'.
#    Time: 0 ns  Iteration: 0  Instance: /syncountw/syn1/jk1 File:   C:/Modeltech_pe_edu_10.4/examples/jkflip.v  
# ** Error (suppressible): (vsim-3053)   C:/Modeltech_pe_edu_10.4/examples/syncounter.v(9): Illegal output or inout port   connection for port 'q'.  
#    Time: 0 ns  Iteration: 0  Instance: /syncountw/syn1/jk2 File:   C:/Modeltech_pe_edu_10.4/examples/jkflip.v  
# ** Error (suppressible): (vsim-3053)   C:/Modeltech_pe_edu_10.4/examples/syncounter.v(9): Illegal output or inout port   connection for port 'qbar'.  
#    Time: 0 ns  Iteration: 0  Instance: /syncountw/syn1/jk2 File:   C:/Modeltech_pe_edu_10.4/examples/jkflip.v

Greg Greg · Accepted Answer · 2015-02-18T04:24:46

qa, qb, qabar, & qbbar are declared as reg, they should be wire. The reg type is for signals assigned by procedural blocks (i.e.: initial & always) in the scope of the current module.

var1 is assigned, but never declared.

Change:

reg qa,qb,qabar,qbbar,overflow;  
//var1 = qa;

To:

reg overflow;  
wire var1;

_{FYI: you forgot to assign qbar a value}

Verilog sync counter

1 Answers